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jerralph / riscv-vip

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
Apache License 2.0
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Whitebox register file and associate register values with instructions #10

Closed jerralph closed 6 years ago

jerralph commented 6 years ago

Create a whitebox interface for monitoring the register values in the register file. Associate the values of register referenced from an instruction with the values observed/used for the instruction. This is useful for coverage and trace.

jerralph commented 6 years ago

Master now has this. Works for Questa but CI is reporting some issues with ius that are under debug.

jerralph commented 6 years ago

Integrated and working as of v0.2.0