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jerralph / riscv-vip

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
Apache License 2.0
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Display the cycle count for instructions #11

Closed jerralph closed 6 years ago

jerralph commented 6 years ago

For the number of cycles between instructions a cycle field has been introduced into instructions. This should be displayed along with the other instruction info by the inst.to_string() method.

jerralph commented 6 years ago

done as of 5ea9102a3861adb990555cc09219f272a7531811. Have yet to run a full regression, I expect this to break a test or two

jerralph commented 6 years ago

Regression working now.

This was the test or two I was mentioning https://github.com/jerralph/riscv-vip/commit/118e5d26e5f570001b30d3c01e571eb4c0337875#diff-1f11fc9b0e3fad4b72403a85f3344d0f