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jerralph / riscv-vip

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
Apache License 2.0
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Update inst_history to be per core in uvm env #12

Open jerralph opened 5 years ago

jerralph commented 5 years ago

A reminder to self to do this. For now, to get things working with a single core solution it was not done on a per-core basis.

muneebullashariff commented 5 years ago

Hi Jerralph,

My name is Muneeb and I am from India. I am a Tech Lead with more than 4 years of experience in Front-end verification having expertise in SystemVerilog and UVM. Also, I have good knowledge of computer architecture.

I came across your project on VIP for RISC-V and its sounds amazing. I think with my knowledge I can contribute to this great project.

I would like to talk to you with this regard. Please do contact me on my email id: muneeb.mirafra@gmail.com.

I'll be looking forward to your humble response.

Regards, Muneeb

jerralph commented 5 years ago

Hi Muneeb, Thanks for reaching out. I will email you directly to continue the conversation. Cheers, Jeremy

muneebullashariff commented 5 years ago

Many thanks for your reply, Jeremy.

I am super excited to collaborate with you on this project.

Regards, Muneeb

On Wed, Oct 31, 2018 at 11:02 PM Jeremy Ralph notifications@github.com wrote:

Hi Muneeb, Thanks for reaching out. I will email you directly to continue the conversation. Cheers, Jeremy

— You are receiving this because you commented. Reply to this email directly, view it on GitHub https://github.com/jerralph/riscv-vip/issues/12#issuecomment-434774396, or mute the thread https://github.com/notifications/unsubscribe-auth/APL1T0tI7CqnRm6ntpx8jpeg-VpH8hy1ks5uqd6VgaJpZM4XKohu .

-- Regards Muneeb Ulla Shariff muneebullashariff@gmail.com