Unit test the rs1/rs2 bins cgs.

jerralph / riscv-vip

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug

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Unit test the rs1/rs2 bins cgs. #15

Open jerralph opened 5 years ago

jerralph commented 5 years ago

These covergroups are one of the few that are not unit tested, and of course if it's not tested it has bugs. Issue 6333684fda694d9e76f2da32f55d4573badd4a2d shows a bug in this where bins was used where ignore_bins was meant. I found it while looking at coverage reports.

jerralph commented 5 years ago

Fix for 6333684fda694d9e76f2da32f55d4573badd4a2d was wrong and next attempt, 8d9a12ba7baa1be0e5154353305810f807d1503a, looks good so far