jerralph / riscv-vip

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
Apache License 2.0
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Flatten the src/uvm/sv_to_uvm directory tree #24

Open jerralph opened 5 years ago

jerralph commented 5 years ago

With the all-uvm-dev branch and the associated milestone, everything is going to be uvm. Remove the un-needed uvm dir and sv_to_uvm from the directory structure.