For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
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Validate all-uvm-dev with scr1 demo before merging to master #25
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jerralph opened 5 years ago
Validate that this branch https://github.com/jerralph/riscv-vip/tree/all-uvm-dev once mostly done with the following milestone https://github.com/jerralph/riscv-vip/milestone/1 will work with the following repo (on a new branch created there): https://github.com/jerralph/riscv-vip-scr1-demo