jerralph / riscv-vip

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
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Error #3

Closed alvinkallely closed 6 years ago

alvinkallely commented 6 years ago

I tried to run code in riviera

It’s throw some errors ERROR VCP5190 “cannot find match for key imm in structure. “ “ ../riscv_vip/src/./instruction_unit_test.sv” 137 1 ERROR VCP5190 “cannot find match for key imm in structure. “ “ ../riscv_vip/src/./instruction_unit_test.sv” 138 1 ERROR VCP5190 “cannot find match for key funct7 in structure. “ “ ../riscv_vip/src/./instruction_unit_test.sv” 139 1

Could you help?

jerralph commented 6 years ago

Thanks Alvin for trying the riscv-vip with Riviera. I have not tried this and I'm not sure if I can get access to that simulator. I'm not sure if it supports the same subset of the SystemVerilog LRM that Cadence and Mentor simulators do. Riscv-vip does work with Cadence and Mentor simulators and I develop and test with those. I'm on vacation currently, but will look into Riviera and the issue you are mentioning when I'm back and have some time. You may also want to check with Aldec support and point them to this repository to see what they say. In the mean time, if you have any more information you can provide or if you find some work-arounds, please report back.

rhotchki commented 6 years ago

I explored this code using EDA playground. And I may have a workaround for the build error. I can look at adding this code as a commit, but it would need to be accepted as a pull request, so I offer it here as a quick workaround.

If the following code at lines 137-139:

      insts[0] = i_inst_t'{imm:99    ,rs1:2,   funct3:3,   rd:1, op:LOAD};
      insts[1] = i_inst_t'{imm:'hFF  ,rs1:1,   funct3:2,   rd:5, op:SYSTEM};
      insts[2] = r_inst_t'{funct7:0, rs2:1, rs1:1, funct3:2, rd:2, op:OP};

Are replaced with:

      insts[0] = create_i_inst(._imm(99), ._rs1(2),
                               ._funct3(3), ._rd(1), ._op(LOAD));
      insts[1] = create_i_inst(._imm('hFF), ._rs1(1),
                               ._funct3(2), ._rd(5), ._op(SYSTEM));
      insts[2] = create_r_inst(._funct7(0), ._rs2(1), 
                               ._rs1(1), ._funct3(2), ._rd(2), ._op(OP));

And then the following two functions are added to the end of the file (within the module, so before endmodule)

function i_inst_t create_i_inst(imm_low_t _imm, regsel_t _rs1, funct3_t _funct3, regsel_t _rd, opcode_t _op);
    i_inst_t _i_inst;

    _i_inst.imm = _imm;
    _i_inst.rs1 = _rs1;
    _i_inst.funct3 = _funct3;
    _i_inst.rd = _rd;
    _i_inst.op = _op;

    return _i_inst;
  endfunction

  function i_inst_t create_r_inst(funct7_t _funct7,
                                  regsel_t _rs2,
                                  regsel_t _rs1,
                                  funct3_t _funct3,
                                  regsel_t _rd,
                                  opcode_t _op);
    r_inst_t _r_inst;

    _r_inst.funct7 = _funct7;
    _r_inst.rs2 = _rs2;
    _r_inst.rs1 = _rs1;
    _r_inst.funct3 = _funct3;
    _r_inst.rd = _rd;
    _r_inst.op = _op; 
    return _r_inst;
  endfunction
jerralph commented 6 years ago

Ok, I'm back from vacation this week and looking at this in more detail.

Thanks @rhotchki for your workaround/fix, I'll work to pull that into this repo! @alvinkallely, have you had a chance to try this fix?