jerralph / riscv-vip

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
Apache License 2.0
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Compile errors in VCS #5

Closed kencycheng closed 6 years ago

kencycheng commented 6 years ago

There will be 6 compile errors when running the riscv_vip in VCS even in the latest release version.

Error-[NYI] Not Yet Implemented
instruction.svh, 254
  Feature is not yet supported: expression other than coverpoint label as 
  coverpoint bin value.            
   i32s_insts_cp : coverpoint inst {
      bins s_insts[] = S_INSTS;
   }

I put all the stuffs at (https://www.edaplayground.com/x/5reM). Cheers!

jerralph commented 6 years ago

Thanks @kencycheng for reporting this. Unfortunately I don't currently have a license for VCS. I do ensure it works with Mentor Questa and Cadence IUS and regress with these. I'll see what I can do to get this working with VCS via EDA playground. If anyone has VCS licenses and has patches / pull requests for modifications to support VCS that would be great.

kencycheng commented 6 years ago

I took a try to replace the dynamic array S_INSTS by {SB, SH, SW}. It works.

   i32s_insts_cp : coverpoint inst {
      bins s_insts[] = S_INSTS;
   }
 i32s_insts_cp : coverpoint inst {
      bins s_insts[] = {SB, SH, SW};
 }
jerralph commented 6 years ago

Thanks @kencycheng for this VCS workaround to incorporate.

Feel free to send pull requests for any VCS workarounds. I had a look at your EDAplayground example but need to get setup there to run, which I do plan to do.

jerralph commented 6 years ago

This is fixed now in master as of 473e8657d70b2262b4e7f5b3769e8396bed29ade I used your recommend technique to fix, @kencycheng; however, I inserted a layer of `defines to allow the enum and bins to be defined from the same single source.