fix vcs compiling errors

jerralph / riscv-vip

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug

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fix vcs compiling errors #6

Closed kencycheng closed 6 years ago

kencycheng commented 6 years ago

There are six compiling errors when we compile the risvc vip with VCS. The error message says "Not implement yet". It is because Systemverilog starts to support put arrays on the right side in 2012 LRM. VCS has not supported the syntax yet.
The fix is simply to expand the array in the bins statements
This can be revisited when VCS support this feature. That would make code cleaner.

jerralph commented 6 years ago

Hi @kencycheng Sorry for the delay in addressing this. I have reproduced and verified your fix in EDA Playground. I did, however, change a few things so there is a single source for the list of instructions for the enums and the coverage bins using `defines. This release has the fixes: https://github.com/jerralph/riscv-vip/commit/473e8657d70b2262b4e7f5b3769e8396bed29ade