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jerralph / riscv-vip

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
Apache License 2.0
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Associate rd values for completed instructions #8

Closed jerralph closed 6 years ago

jerralph commented 6 years ago

In the write-back pipeline stage, when an instruction is complete, associate the rd value written back with the instruction and display it in the to_string()/trace.

jerralph commented 6 years ago

This was added and is working for v0.2.0 (56dab8e32b05f0fabdf456c6b781507cd279cf89) and later