search

jerralph / riscv-vip

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
Apache License 2.0
54 stars 30 forks source link

associate branch/jump addresses with associated instruction after completion #9

Open jerralph opened 6 years ago

jerralph commented 6 years ago

This can provide some nice coverage and helps with trace/debug