Add RISC-V support for simd_cast

[ita-sc]

Hi

This patches add extends support for simd_cast for RISC-V. Also I'm fixing combine and to_logical functions for RISC-V and turn on wide api test, to be sure that combine and slice works fine.

Cast from logical to wide still prohibited.

[DenisYaroshevskiy]

Here is what I suggest with tests.

Globally

• all tests below 256 bytes.
• 16 doubles, 32 doubles, 16 uint64s, 32 uint64s

The rest is left untested.

[ita-sc]

Here is what I suggest with tests

Yep, I will try. By the way, what memory consumption for test will be ok for EVE CI?

[DenisYaroshevskiy]

No idea. We run eve ci on boxes we own, it should be not too bad as far as the limits go.

[jfalcou]

FYI, my if_else merge was incorrect and I pushed a correction, it should fix the fails.

[ita-sc]

Gentle ping

[DenisYaroshevskiy]

In case the comment get's lost - we shouldn't filter the types for this simple test. Because if in this simple test it's a problem, it's going to be a problem for every test. More details in the big coment.

[ita-sc]

Updated review. Now I reduce globally types in eve::test::simd::all_types and similar for these rules:

• all wide types with size below or equal 512 bits (for vlen=128 they use lmul=4)
• for double, int64_t, uint64_t also check expected cardinals (for vlen=128 their size will be 8 128 = 1024) and combined types with cardinals == 2 expected cardinals.

Note: you requested to check all types with size bellow 256 bytes, but for vlen=128 all wide will be smaller: max size for "physical" register will be 128*8 / 8 = 128 bytes, so we have nothing for filtering.

[DenisYaroshevskiy]

Aggregation! We have aggregation! It's important to check support for emulation of 2 registers togerther

[DenisYaroshevskiy]

Eve emulates bigger than native registers if you ask for it.

[DenisYaroshevskiy]

will merge after ci