Questions about Synthesis

[ShawnHSH]

I am new to accelerator design and very excited to get in touch with this fantastic work. I have some questions hoping you can kindly help. I was trying your synthesis sample in readme, dc_shell -f 14nm_sg.tcl -x "set top_module mac_lane". But it turned out the following are missing: filter.sv im2col_cpu_add_32dEe.v im2col_cpu_sdiv_3fYi.v max_pooling.sv pooling.sv bn_forward.sv bn_backward.sv im2col_cpu_add_32g8j.v im2col_cpu_sub_32eOg.v mean.sv im2col_cpu.v im2col_cpu_data_col.v mean_pooling.sv im2col_cpu_add_31hbi.v im2col_cpu_add_32bkb.v im2col_cpu_mul_32cud.v top.sv.

So I then deleted them from the analyze command. it worked for a while but failed to write: write_file -format verilog -output "$netlist_path/$netlist_file" Error: Can't open export file '/home/shawn/Documents/acceltran/synthesis/netlists/mac_lane.v'. (EXPT-4) Error: Write command failed. (UID-25) 0 set filename [format "%s%s" $top_module ".ddc"] mac_lane.ddc write -f ddc -hier -output "$ddc_path/$filename" Error: Unable to open DDC file './ddc/mac_lane.ddc' for writing. (DDC-1) Error: Write command failed. (UID-25)

I wonder if there are ways to fix these errors and whether the above file missing affects the correctness of the synthesis process. There are also some warnings I cannot tell if they are important.

Warning: In design 'mac_lane', cell 'B_16' does not drive any nets. (LINT-1) Warning: In design 'stochastic_rounding_IL4_FL16', cell 'C140' does not drive any nets. (LINT-1) Warning: In design 'stochastic_rounding_IL4_FL16', cell 'B_4' does not drive any nets. (LINT-1) Warning: In design 'SiLU_IL4_FL16', cell 'C389' does not drive any nets. (LINT-1) Warning: In design 'SiLU_IL4_FL16', cell 'C392' does not drive any nets. (LINT-1) Warning: In design 'mul_IL4_FL16', port 'clk' is not connected to any nets. (LINT-28) Warning: In design 'mul_IL4_FL16', port 'reset' is not connected to any nets. (LINT-28) Warning: In design 'ReLU_IL4_FL16', port 'clk' is not connected to any nets. (LINT-28) Warning: In design 'ReLU_IL4_FL16', port 'reset' is not connected to any nets. (LINT-28) Warning: In design 'SiLU_IL4_FL16', port 'clk' is not connected to any nets. (LINT-28) Warning: In design 'SiLU_IL4_FL16', port 'reset' is not connected to any nets. (LINT-28) Warning: In design 'add_WL40', port 'clk' is not connected to any nets. (LINT-28) Warning: In design 'add_WL40', port 'reset' is not connected to any nets. (LINT-28) Warning: In design 'add_WL41', port 'clk' is not connected to any nets. (LINT-28) Warning: In design 'add_WL41', port 'reset' is not connected to any nets. (LINT-28) Warning: In design 'add_WL42', port 'clk' is not connected to any nets. (LINT-28) Warning: In design 'add_WL42', port 'reset' is not connected to any nets. (LINT-28) Warning: In design 'add_WL43', port 'clk' is not connected to any nets. (LINT-28) Warning: In design 'add_WL43', port 'reset' is not connected to any nets. (LINT-28) Warning: Target library contains no replacement for register 'ReLU_0/f_reg[0]' (FFGEN). (TRANS-4) ... Warning: Design 'mac_lane' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134) Warning: Design 'mac_lane' inherited license information from design 'mul_IL4_FL16_15_DW_mult_tc_J9_0'. (DDB-74) Warning: Target library contains no replacement for register 'ReLU_0/f_reg[18]' (FFGEN). (TRANS-4) ... Warning: Target library contains no replacement for register 'SiLU_0/f_reg[0]' (FFGEN). (TRANS-4)

[shikhartuli]

We have fixed this in 68dc2ae.