jhshi / openofdm

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
http://openofdm.rtfd.io
Apache License 2.0
367 stars 188 forks source link

rotate.v has 9 clock delay #1

Open jinsanko opened 6 years ago

jinsanko commented 6 years ago

Why adds 4 clock delay in the data inputs of rotate.v? one delayT module with 4 clock delay for data and one delayT module with 4 clock delay for the strobe. Thank.

Best regards

Jinsan Ko