testing on USRP

[weiliu1011]

Dear Jingshi, I am a researcher from Ghent University, your open source project looks very interesting, and we'd like to test it on USRP N210. Though I am not able to synthesize successfully. Could you help me with it? Below is a few details:

I followed your instruction in "Integration with USRP", modified the Makefile.N210R4 into a customized version, added the Verilog macro, but instead of commenting out the CUSTOM_SRC, I used it to specify the custom_dsp_rx.v file, I could compile a bitstream for N210 successfully at this point

Then I instantiated dot11.v module in custom_dsp_rx.v, and also added the verilog files listed in dot11_modules.list in the CUSTOM_SRC, after this the compilation fails and complaining some unresolved names. I checked that all of them are the ones with Xilinx cores.

As a 3rd step I tried to add ngc files of the Xilinx cores located in the openofdm/verilog/coregen folder. Though then Xilinx ISE12.2 compiler seems to enter a deadlock status, and never finishes the compilation.

So help me to find what is the correct way of adding the source file with Xilinx cores to the usrp2 project?

Thank you in advance, Wei

[MarlonBedoya]

Could you resolve your problem? I have the same unresolved issue :(

[weiliu1011]

No, we eventually went to the zynq fpga with AD9361 frontend, you can check https://github.com/open-sdr/openwifi for more details