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jhshi / openofdm

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
http://openofdm.rtfd.io
Apache License 2.0
354 stars 183 forks source link

Simulation of full HDL #7

Open hyanki opened 4 years ago

hyanki commented 4 years ago

Hi i have doubt that can i simulate complete design on modelsim? regards hyanki

hyanki commented 4 years ago

Hi jshi what are the steps to simulate in icarus verilog. Regards Hyanki

hyanki commented 3 years ago

Hi i In demodulater.v file why scaling factor is taken 1024 though input is in 16 bit? What is data format of IQ in 16bit? Regards J S Hyanki

JiaoXianjun commented 3 years ago

if you like, you can simulate via Vivado. our reference: https://github.com/open-sdr/openwifi-hw/issues/17