jjhorton
commented
2 years ago Schematic and Github workflow have been upgraded to kicad 6.0 to support the firmware development
Closed jjhorton closed 2 years ago
jjhorton
commented
2 years ago Schematic and Github workflow have been upgraded to kicad 6.0 to support the firmware development
github-actions[bot]
commented
2 years ago Testing Output:
Coverage Stats:
Reading tracefile logs/coverage.info
|Lines |Functions |Branches
Filename |Rate Num|Rate Num|Rate Num
=========================================================
[/]
top.v |77.8% 9| - 0| - 0
writepixels.v | 100% 79| - 0| - 0
=========================================================
Total:|97.7% 88| - 0| - 0Testing Output:
Coverage Stats:
Reading tracefile logs/coverage.info
|Lines |Functions |Branches
Filename |Rate Num|Rate Num|Rate Num
=========================================================
[/]
top.v |94.0% 67| - 0| - 0
writepixels.v | 100% 88| - 0| - 0
=========================================================
Total:|97.4% 155| - 0| - 0Testing Output:
Coverage Stats:
Reading tracefile logs/coverage.info
|Lines |Functions |Branches
Filename |Rate Num|Rate Num|Rate Num
=========================================================
[/]
top.v |94.0% 67| - 0| - 0
writepixels.v | 100% 88| - 0| - 0
=========================================================
Total:|97.4% 155| - 0| - 0FPGA Place and Route statistics:
Device utilisation:
ICESTORM_LC: 210/ 5280 3%
ICESTORM_RAM: 1/ 30 3%
SB_IO: 18/ 96 18%
SB_GB: 3/ 8 37%
ICESTORM_PLL: 0/ 1 0%
SB_WARMBOOT: 0/ 1 0%
ICESTORM_DSP: 0/ 8 0%
ICESTORM_HFOSC: 0/ 1 0%
ICESTORM_LFOSC: 0/ 1 0%
SB_I2C: 0/ 2 0%
SB_SPI: 0/ 2 0%
IO_I3C: 0/ 2 0%
SB_LEDDA_IP: 0/ 1 0%
SB_RGBA_DRV: 0/ 1 0%
ICESTORM_SPRAM: 0/ 4 0%
Max frequency for clock 'writepixels.sys_clk_$glb_clk': 78.39 MHz (PASS at 12.00 MHz)Testing Output:
Coverage Stats:
Reading tracefile logs/coverage.info
|Lines |Functions |Branches
Filename |Rate Num|Rate Num|Rate Num
=========================================================
[/]
top.v |94.0% 67| - 0| - 0
writepixels.v | 100% 88| - 0| - 0
=========================================================
Total:|97.4% 155| - 0| - 0FPGA Place and Route statistics:
Device utilisation:
ICESTORM_LC: 239/ 5280 4%
ICESTORM_RAM: 1/ 30 3%
SB_IO: 18/ 96 18%
SB_GB: 4/ 8 50%
ICESTORM_PLL: 0/ 1 0%
SB_WARMBOOT: 0/ 1 0%
ICESTORM_DSP: 0/ 8 0%
ICESTORM_HFOSC: 0/ 1 0%
ICESTORM_LFOSC: 0/ 1 0%
SB_I2C: 0/ 2 0%
SB_SPI: 0/ 2 0%
IO_I3C: 0/ 2 0%
SB_LEDDA_IP: 0/ 1 0%
SB_RGBA_DRV: 0/ 1 0%
ICESTORM_SPRAM: 0/ 4 0%
Max frequency for clock 'writepixels.sys_clk_$glb_clk': 72.24 MHz (PASS at 12.00 MHz)Testing Output:
Coverage Stats:
Reading tracefile logs/coverage.info
|Lines |Functions |Branches
Filename |Rate Num|Rate Num|Rate Num
=========================================================
[/]
top.v |94.9% 79| - 0| - 0
writepixels.v | 100% 113| - 0| - 0
=========================================================
Total:|97.9% 192| - 0| - 0FPGA Place and Route statistics:
Device utilisation:
ICESTORM_LC: 494/ 5280 9%
ICESTORM_RAM: 1/ 30 3%
SB_IO: 18/ 96 18%
SB_GB: 8/ 8 100%
ICESTORM_PLL: 0/ 1 0%
SB_WARMBOOT: 0/ 1 0%
ICESTORM_DSP: 0/ 8 0%
ICESTORM_HFOSC: 0/ 1 0%
ICESTORM_LFOSC: 0/ 1 0%
SB_I2C: 0/ 2 0%
SB_SPI: 0/ 2 0%
IO_I3C: 0/ 2 0%
SB_LEDDA_IP: 0/ 1 0%
SB_RGBA_DRV: 0/ 1 0%
ICESTORM_SPRAM: 0/ 4 0%
Max frequency for clock 'CLK$SB_IO_IN_$glb_clk': 38.28 MHz (PASS at 12.00 MHz)Testing Output:
Coverage Stats:
Reading tracefile logs/coverage.info
|Lines |Functions |Branches
Filename |Rate Num|Rate Num|Rate Num
=========================================================
[/]
top.v |94.9% 79| - 0| - 0
writepixels.v | 100% 113| - 0| - 0
=========================================================
Total:|97.9% 192| - 0| - 0FPGA Place and Route statistics:
Device utilisation:
ICESTORM_LC: 491/ 5280 9%
ICESTORM_RAM: 1/ 30 3%
SB_IO: 18/ 96 18%
SB_GB: 8/ 8 100%
ICESTORM_PLL: 0/ 1 0%
SB_WARMBOOT: 0/ 1 0%
ICESTORM_DSP: 0/ 8 0%
ICESTORM_HFOSC: 0/ 1 0%
ICESTORM_LFOSC: 0/ 1 0%
SB_I2C: 0/ 2 0%
SB_SPI: 0/ 2 0%
IO_I3C: 0/ 2 0%
SB_LEDDA_IP: 0/ 1 0%
SB_RGBA_DRV: 0/ 1 0%
ICESTORM_SPRAM: 0/ 4 0%
Max frequency for clock 'writepixels.sys_clk_$glb_clk': 38.65 MHz (PASS at 12.00 MHz)Testing Output:
Coverage Stats:
Reading tracefile logs/coverage.info
|Lines |Functions |Branches
Filename |Rate Num|Rate Num|Rate Num
=========================================================
[/]
top.v |96.2% 79| - 0| - 0
writepixels.v | 100% 113| - 0| - 0
=========================================================
Total:|98.4% 192| - 0| - 0FPGA Place and Route statistics:
Device utilisation:
ICESTORM_LC: 491/ 5280 9%
ICESTORM_RAM: 1/ 30 3%
SB_IO: 18/ 96 18%
SB_GB: 8/ 8 100%
ICESTORM_PLL: 0/ 1 0%
SB_WARMBOOT: 0/ 1 0%
ICESTORM_DSP: 0/ 8 0%
ICESTORM_HFOSC: 0/ 1 0%
ICESTORM_LFOSC: 0/ 1 0%
SB_I2C: 0/ 2 0%
SB_SPI: 0/ 2 0%
IO_I3C: 0/ 2 0%
SB_LEDDA_IP: 0/ 1 0%
SB_RGBA_DRV: 0/ 1 0%
ICESTORM_SPRAM: 0/ 4 0%
Max frequency for clock 'writepixels.sys_clk_$glb_clk': 41.00 MHz (PASS at 12.00 MHz)
Create a firmware build to run on icebreaker