Closed jjhorton closed 2 years ago
Testing Output: Coverage Stats:
Reading tracefile logs/coverage.info
|Lines |Functions |Branches
Filename |Rate Num|Rate Num|Rate Num
==================================================
[/]
blinky.v | 100% 15| - 0| - 0
==================================================
Total:| 100% 15| - 0| - 0
FPGA Place and Route statistics:
Device utilisation:
ICESTORM_LC: 40/ 5280 0%
ICESTORM_RAM: 0/ 30 0%
SB_IO: 9/ 96 9%
SB_GB: 2/ 8 25%
ICESTORM_PLL: 0/ 1 0%
SB_WARMBOOT: 0/ 1 0%
ICESTORM_DSP: 0/ 8 0%
ICESTORM_HFOSC: 0/ 1 0%
ICESTORM_LFOSC: 0/ 1 0%
SB_I2C: 0/ 2 0%
SB_SPI: 0/ 2 0%
IO_I3C: 0/ 2 0%
SB_LEDDA_IP: 0/ 1 0%
SB_RGBA_DRV: 0/ 1 0%
ICESTORM_SPRAM: 0/ 4 0%
Max frequency for clock 'CLK$SB_IO_IN_$glb_clk': 74.76 MHz (PASS at 12.00 MHz)
Add build to the ECP5 board with 45k FPGA on Colorlite i9 board