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jjhorton / PMod

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7seg pcb fab action update to V6 #68

Closed jjhorton closed 2 years ago

github-actions[bot] commented 2 years ago

Testing Output: Coverage Stats:

Reading tracefile logs/coverage.info
                   |Lines       |Functions  |Branches    
Filename           |Rate     Num|Rate    Num|Rate     Num
=========================================================
[/]
top.v              |94.0%     83|    -     0|    -      0
writepixels.v      | 100%    113|    -     0|    -      0
=========================================================
             Total:|97.4%    196|    -     0|    -      0
github-actions[bot] commented 2 years ago

FPGA Place and Route statistics:


 Device utilisation:
             ICESTORM_LC:   398/ 5280     7%
            ICESTORM_RAM:     0/   30     0%
                   SB_IO:    26/   96    27%
                   SB_GB:     8/    8   100%
            ICESTORM_PLL:     0/    1     0%
             SB_WARMBOOT:     0/    1     0%
            ICESTORM_DSP:     0/    8     0%
          ICESTORM_HFOSC:     0/    1     0%
          ICESTORM_LFOSC:     0/    1     0%
                  SB_I2C:     0/    2     0%
                  SB_SPI:     0/    2     0%
                  IO_I3C:     0/    2     0%
             SB_LEDDA_IP:     0/    1     0%
             SB_RGBA_DRV:     0/    1     0%
          ICESTORM_SPRAM:     0/    4     0%

 Max frequency for clock 'writepixels.sys_clk_$glb_clk': 40.32 MHz (PASS at 12.00 MHz)
github-actions[bot] commented 2 years ago

Testing Output: Coverage Stats:

Reading tracefile logs/coverage.info
                   |Lines       |Functions  |Branches    
Filename           |Rate     Num|Rate    Num|Rate     Num
=========================================================
[/]
top.v              |94.0%     83|    -     0|    -      0
writepixels.v      | 100%    113|    -     0|    -      0
=========================================================
             Total:|97.4%    196|    -     0|    -      0
github-actions[bot] commented 2 years ago

FPGA Place and Route statistics:


 Device utilisation:
             ICESTORM_LC:   398/ 5280     7%
            ICESTORM_RAM:     0/   30     0%
                   SB_IO:    26/   96    27%
                   SB_GB:     8/    8   100%
            ICESTORM_PLL:     0/    1     0%
             SB_WARMBOOT:     0/    1     0%
            ICESTORM_DSP:     0/    8     0%
          ICESTORM_HFOSC:     0/    1     0%
          ICESTORM_LFOSC:     0/    1     0%
                  SB_I2C:     0/    2     0%
                  SB_SPI:     0/    2     0%
                  IO_I3C:     0/    2     0%
             SB_LEDDA_IP:     0/    1     0%
             SB_RGBA_DRV:     0/    1     0%
          ICESTORM_SPRAM:     0/    4     0%

 Max frequency for clock 'writepixels.sys_clk_$glb_clk': 40.32 MHz (PASS at 12.00 MHz)
github-actions[bot] commented 2 years ago

Testing Output: Coverage Stats:

Reading tracefile logs/coverage.info
                   |Lines       |Functions  |Branches    
Filename           |Rate     Num|Rate    Num|Rate     Num
=========================================================
[/]
top.v              |94.0%     83|    -     0|    -      0
writepixels.v      | 100%    113|    -     0|    -      0
=========================================================
             Total:|97.4%    196|    -     0|    -      0
github-actions[bot] commented 2 years ago

FPGA Place and Route statistics:


 Device utilisation:
             ICESTORM_LC:   398/ 5280     7%
            ICESTORM_RAM:     0/   30     0%
                   SB_IO:    26/   96    27%
                   SB_GB:     8/    8   100%
            ICESTORM_PLL:     0/    1     0%
             SB_WARMBOOT:     0/    1     0%
            ICESTORM_DSP:     0/    8     0%
          ICESTORM_HFOSC:     0/    1     0%
          ICESTORM_LFOSC:     0/    1     0%
                  SB_I2C:     0/    2     0%
                  SB_SPI:     0/    2     0%
                  IO_I3C:     0/    2     0%
             SB_LEDDA_IP:     0/    1     0%
             SB_RGBA_DRV:     0/    1     0%
          ICESTORM_SPRAM:     0/    4     0%

 Max frequency for clock 'writepixels.sys_clk_$glb_clk': 40.32 MHz (PASS at 12.00 MHz)
github-actions[bot] commented 2 years ago

Testing Output: Coverage Stats:

Reading tracefile logs/coverage.info
                   |Lines       |Functions  |Branches    
Filename           |Rate     Num|Rate    Num|Rate     Num
=========================================================
[/]
top.v              |94.0%     83|    -     0|    -      0
writepixels.v      | 100%    113|    -     0|    -      0
=========================================================
             Total:|97.4%    196|    -     0|    -      0
github-actions[bot] commented 2 years ago

FPGA Place and Route statistics:


 Device utilisation:
             ICESTORM_LC:   398/ 5280     7%
            ICESTORM_RAM:     0/   30     0%
                   SB_IO:    26/   96    27%
                   SB_GB:     8/    8   100%
            ICESTORM_PLL:     0/    1     0%
             SB_WARMBOOT:     0/    1     0%
            ICESTORM_DSP:     0/    8     0%
          ICESTORM_HFOSC:     0/    1     0%
          ICESTORM_LFOSC:     0/    1     0%
                  SB_I2C:     0/    2     0%
                  SB_SPI:     0/    2     0%
                  IO_I3C:     0/    2     0%
             SB_LEDDA_IP:     0/    1     0%
             SB_RGBA_DRV:     0/    1     0%
          ICESTORM_SPRAM:     0/    4     0%

 Max frequency for clock 'writepixels.sys_clk_$glb_clk': 40.32 MHz (PASS at 12.00 MHz)
github-actions[bot] commented 2 years ago

Testing Output: Coverage Stats:

Reading tracefile logs/coverage.info
                   |Lines       |Functions  |Branches    
Filename           |Rate     Num|Rate    Num|Rate     Num
=========================================================
[/]
top.v              |94.0%     83|    -     0|    -      0
writepixels.v      | 100%    113|    -     0|    -      0
=========================================================
             Total:|97.4%    196|    -     0|    -      0
github-actions[bot] commented 2 years ago

FPGA Place and Route statistics:


 Device utilisation:
             ICESTORM_LC:   398/ 5280     7%
            ICESTORM_RAM:     0/   30     0%
                   SB_IO:    26/   96    27%
                   SB_GB:     8/    8   100%
            ICESTORM_PLL:     0/    1     0%
             SB_WARMBOOT:     0/    1     0%
            ICESTORM_DSP:     0/    8     0%
          ICESTORM_HFOSC:     0/    1     0%
          ICESTORM_LFOSC:     0/    1     0%
                  SB_I2C:     0/    2     0%
                  SB_SPI:     0/    2     0%
                  IO_I3C:     0/    2     0%
             SB_LEDDA_IP:     0/    1     0%
             SB_RGBA_DRV:     0/    1     0%
          ICESTORM_SPRAM:     0/    4     0%

 Max frequency for clock 'writepixels.sys_clk_$glb_clk': 40.32 MHz (PASS at 12.00 MHz)
github-actions[bot] commented 2 years ago

Testing Output: Coverage Stats:

Reading tracefile logs/coverage.info
                   |Lines       |Functions  |Branches    
Filename           |Rate     Num|Rate    Num|Rate     Num
=========================================================
[/]
top.v              |94.0%     83|    -     0|    -      0
writepixels.v      | 100%    113|    -     0|    -      0
=========================================================
             Total:|97.4%    196|    -     0|    -      0
github-actions[bot] commented 2 years ago

FPGA Place and Route statistics:


 Device utilisation:
             ICESTORM_LC:   398/ 5280     7%
            ICESTORM_RAM:     0/   30     0%
                   SB_IO:    26/   96    27%
                   SB_GB:     8/    8   100%
            ICESTORM_PLL:     0/    1     0%
             SB_WARMBOOT:     0/    1     0%
            ICESTORM_DSP:     0/    8     0%
          ICESTORM_HFOSC:     0/    1     0%
          ICESTORM_LFOSC:     0/    1     0%
                  SB_I2C:     0/    2     0%
                  SB_SPI:     0/    2     0%
                  IO_I3C:     0/    2     0%
             SB_LEDDA_IP:     0/    1     0%
             SB_RGBA_DRV:     0/    1     0%
          ICESTORM_SPRAM:     0/    4     0%

 Max frequency for clock 'writepixels.sys_clk_$glb_clk': 40.32 MHz (PASS at 12.00 MHz)