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Workflow on merge #83

Closed jjhorton closed 1 year ago

jjhorton commented 1 year ago

Add all kicad 6 based workflows to run on the schedule of once a day at 8AM

github-actions[bot] commented 1 year ago

Testing Output: Coverage Stats:

Reading tracefile logs/coverage.info
                   |Lines       |Functions  |Branches    
Filename           |Rate     Num|Rate    Num|Rate     Num
=========================================================
[/]
top.v              |96.2%     80|    -     0|    -      0
writepixels.v      | 100%    113|    -     0|    -      0
=========================================================
             Total:|98.4%    193|    -     0|    -      0
github-actions[bot] commented 1 year ago

Testing Output: Coverage Stats:

Reading tracefile logs/coverage.info
                   |Lines       |Functions  |Branches    
Filename           |Rate     Num|Rate    Num|Rate     Num
=========================================================
[/]
top.v              |94.0%     83|    -     0|    -      0
writepixels.v      | 100%    113|    -     0|    -      0
=========================================================
             Total:|97.4%    196|    -     0|    -      0
github-actions[bot] commented 1 year ago

Testing Output: Coverage Stats:

Reading tracefile logs/coverage.info
            |Lines       |Functions  |Branches    
Filename    |Rate     Num|Rate    Num|Rate     Num
==================================================
[/]
blinky.v    | 100%     15|    -     0|    -      0
==================================================
      Total:| 100%     15|    -     0|    -      0
github-actions[bot] commented 1 year ago

FPGA Place and Route statistics:


 Device utilisation:
             ICESTORM_LC:   400/ 5280     7%
            ICESTORM_RAM:     0/   30     0%
                   SB_IO:    26/   96    27%
                   SB_GB:     8/    8   100%
            ICESTORM_PLL:     0/    1     0%
             SB_WARMBOOT:     0/    1     0%
            ICESTORM_DSP:     0/    8     0%
          ICESTORM_HFOSC:     0/    1     0%
          ICESTORM_LFOSC:     0/    1     0%
                  SB_I2C:     0/    2     0%
                  SB_SPI:     0/    2     0%
                  IO_I3C:     0/    2     0%
             SB_LEDDA_IP:     0/    1     0%
             SB_RGBA_DRV:     0/    1     0%
          ICESTORM_SPRAM:     0/    4     0%

 Max frequency for clock 'writepixels.sys_clk_$glb_clk': 45.97 MHz (PASS at 12.00 MHz)
github-actions[bot] commented 1 year ago

FPGA Place and Route statistics:


 Device utilisation:
             ICESTORM_LC:   400/ 5280     7%
            ICESTORM_RAM:     0/   30     0%
                   SB_IO:    26/   96    27%
                   SB_GB:     8/    8   100%
            ICESTORM_PLL:     0/    1     0%
             SB_WARMBOOT:     0/    1     0%
            ICESTORM_DSP:     0/    8     0%
          ICESTORM_HFOSC:     0/    1     0%
          ICESTORM_LFOSC:     0/    1     0%
                  SB_I2C:     0/    2     0%
                  SB_SPI:     0/    2     0%
                  IO_I3C:     0/    2     0%
             SB_LEDDA_IP:     0/    1     0%
             SB_RGBA_DRV:     0/    1     0%
          ICESTORM_SPRAM:     0/    4     0%

 Max frequency for clock 'writepixels.sys_clk_$glb_clk': 45.80 MHz (PASS at 12.00 MHz)
github-actions[bot] commented 1 year ago

FPGA Place and Route statistics:


 Device utilisation:
             ICESTORM_LC:    40/ 5280     0%
            ICESTORM_RAM:     0/   30     0%
                   SB_IO:     9/   96     9%
                   SB_GB:     2/    8    25%
            ICESTORM_PLL:     0/    1     0%
             SB_WARMBOOT:     0/    1     0%
            ICESTORM_DSP:     0/    8     0%
          ICESTORM_HFOSC:     0/    1     0%
          ICESTORM_LFOSC:     0/    1     0%
                  SB_I2C:     0/    2     0%
                  SB_SPI:     0/    2     0%
                  IO_I3C:     0/    2     0%
             SB_LEDDA_IP:     0/    1     0%
             SB_RGBA_DRV:     0/    1     0%
          ICESTORM_SPRAM:     0/    4     0%

 Max frequency for clock 'CLK$SB_IO_IN_$glb_clk': 74.76 MHz (PASS at 12.00 MHz)
github-actions[bot] commented 1 year ago

FPGA Place and Route statistics:


 Device utilisation:
             ICESTORM_LC:   748/ 5280    14%
            ICESTORM_RAM:     0/   30     0%
                   SB_IO:    18/   96    18%
                   SB_GB:     8/    8   100%
            ICESTORM_PLL:     0/    1     0%
             SB_WARMBOOT:     0/    1     0%
            ICESTORM_DSP:     0/    8     0%
          ICESTORM_HFOSC:     0/    1     0%
          ICESTORM_LFOSC:     0/    1     0%
                  SB_I2C:     0/    2     0%
                  SB_SPI:     0/    2     0%
                  IO_I3C:     0/    2     0%
             SB_LEDDA_IP:     0/    1     0%
             SB_RGBA_DRV:     0/    1     0%
          ICESTORM_SPRAM:     0/    4     0%

 Max frequency for clock 'writepixel.pixel_clk_$glb_clk': 59.51 MHz (PASS at 12.00 MHz)

Coverage Stats:

Reading tracefile logs/coverage.info
                  |Lines       |Functions  |Branches    
Filename          |Rate     Num|Rate    Num|Rate     Num
========================================================
[/]
rxuart.v          |96.6%     58|    -     0|    -      0
top.v             |96.3%     81|    -     0|    -      0
writepixel.v      | 100%     60|    -     0|    -      0
========================================================
            Total:|97.5%    199|    -     0|    -      0