jkiv / shapool-core

FPGA core for SHA256d mining targeting Lattice iCE40 devices.
BSD 3-Clause "New" or "Revised" License
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Alternate interface to COPI1/CIPO1 #12

Closed jkiv closed 3 years ago

jkiv commented 3 years ago

Lattice development boards (e.g. UP5K, ICE40HX8K, MachXO3LF) have an FTDI device configured with an SPI interface (for programming the device in SPI slave mode) and a UART interface, whereas the icepool board has uses two SPI interfaces.

For the sake of using the development boards, is it possible to substitute the second SPI interface, e.g.

jkiv commented 3 years ago

Nah.