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jkiv / shapool-core

FPGA core for SHA256d mining targeting Lattice iCE40 devices.
BSD 3-Clause "New" or "Revised" License
20 stars 7 forks source link

Test device using prototyping MCU. #2

Closed jkiv closed 3 years ago

jkiv commented 5 years ago

Transcribe test cases from verilog to a prototyping MCU (e.g. Arduino) to test SPI and computational capability.

jkiv commented 5 years ago

Additionally, test uploading a bitstream from an MCU.

jkiv commented 3 years ago

Abandoned SAMD21 for icepool. Tests can be over USB/FTDI.