yosys fails to parse sha_unit.v

[jkiv]

Issue with yosys parsing sha_unit.v. Requires more investigation.

$ make make shapool_hx8k_ct256.bin
yosys -p 'synth_ice40 -top top_hx8k -blif shapool_hx8k.blif -abc2 -retime' top_hx8k.v top.v shapool.v sha_unit.v sha_round.v w_expand.v SHA256_K.v difficulty_map.v
[...]
Parsing Verilog input from `sha_unit.v' to AST representation.
Generating RTLIL representation for module `\sha_unit'.
ERROR: Failed to detect width of memory access `\Mt' at sha_unit.v:57!
Makefile:12: recipe for target 'shapool_hx8k.blif' failed
make: *** [shapool_hx8k.blif] Error 1

I set up a new development environment using "apt-get install" whereas I previously built from Github sources.

$ yosys -V
Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os)

It mentions using Verilog-2005 frontend. I'm not sure if I used that in the past, or if it was (somehow) iverilog. All my test code uses iverilog.

[jkiv]

Just needed to define Mt before its use.