jkominek
commented
3 years ago - [x] Need a bit more thermal relief on the passives connected to the top layer copper pour. They're sort of a pain to hand solder.
- [x] C10 (incoming .1uF on the 48V rail) is just a bit too close to J9
- [x] Why did I use different resistor values for R24 (Vref drain) and R9 (/SHDN pullup)? No reason I couldn't just use some arbitrary value in the 2.2k-5k range for both. Pick something I'm using elsewhere (the dividers?) that actually matters and just use that for both, to reduce BOM.
- [x] R0 is unnecessary for draining the big cap now that we've got the voltage divider on +48V, draining 0.5W all the time (huh, maybe i should up the total resistance of the voltage divider)
- [x] Eliminate the need for the +15V supply, by regulating the +48V down to about +24V with an LM317. Should be cheaper than putting the second screw terminal on the board. The op amps can use the +24V directly, and that should be low enough for the 5V regulator feeding the precision voltage reference. Expected current draw on the whole rail is <1mA, as we're just feeding quiescent currents and the op amps are keeping MOSFET gates stable.
- [x] /IRQ line should be pulled down with a transistor, instead of directly attached to a pin.