Open jkougoulos opened 6 years ago
Consider rearranging the PCB layout for TPL5010 according to manufacturer's guidance to avoid parasitic capacitance (paragraph 11.2 of http://www.ti.com/lit/ds/symlink/tpl5010.pdf)
Need to add also bypass X7R 100nF between VDD and GND (paragraph 10)
Consider rearranging the PCB layout for TPL5010 according to manufacturer's guidance to avoid parasitic capacitance (paragraph 11.2 of http://www.ti.com/lit/ds/symlink/tpl5010.pdf)