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Posts Ideas: FPGAs Sistemas empotrado y procesamiento #28

Open jmgomez-IAA opened 5 years ago

jmgomez-IAA commented 5 years ago

International Symposium on Field-Programmable Gate Arrays

jmgomez-IAA commented 5 years ago

Web con modelos vhdl

https://freemodelfoundry.com/model_list.php

jmgomez-IAA commented 4 years ago

Cmod A7: Breadboardable Artix-7 FPGA Module

The Digilent Cmod A7 is a small, breadboard friendly 48-pin DIP form factor board built around a Xilinx Artix-7 FPGA. The board also includes a USB-JTAG programming circuit, USB-UART bridge, clock source, Pmod host connector, SRAM, Quad-SPI Flash, and basic I/O devices

Features:

Reference Design

The projects does not include the project file, there is a tcl script on the project folder that generates it. In order to run it, open Xilinx Vivado, and tools -> Run TCL SCript

https://github.com/Digilent/digilent-vivado-scripts

Master Constraint file

https://raw.githubusercontent.com/Digilent/CmodA7/master/Resources/XDC/CmodA7_Master.xdc

CMOD-A7 GPIO

There is a problem with the clk_wiz_0 ip core, which is deprecated on Vivado 2019.2 and requires major changes when updated. The solution is to update the ip core,, on the sources , select IP Source, right click and select Report Status. Then select clk_wiz_0 and update Error ref

VHDL Design

References

  1. VHDL Cookbook
  2. VHDL Tutorial: Learn by Example -- by Weijun Zhang, July 2001
  3. Embedded System Design: A Unified Hardware/Software Introduction Incluye slides con descripciones de como hacer un procesador.

GRLIB

Download GRLIB from Gaisler:

wget  https://www.gaisler.com/products/grlib/grlib-gpl-2019.4-b4246.tar.gz
tar xvf grlib-gpl-2019.4-b4246.tar.gz

Para compilar se copia el directorio del port dentro de la GRLIB. git clone https://github.com/cajt/cmod-a7-35t_leon3.git

Copiamos el del diseno y de la tarjeta dentro de grlib. cd grlib-gpl-2019.4-b4246/designs/leon3-digilent-cmoda7-xc7a35t/

make vivado

Dentro de grlib-gpl-2019.4-b4246/designs/leon3-digilent-cmoda7-xc7a35t/

References

jmgomez-IAA commented 4 years ago

Vivado 2019.2 Install ArchLinux

Para instalar Vivado se requiere:

https://aur.archlinux.org/packages/xilinx-vivado-dummy/

Es posible que pacman -S xilinx-vivado-dummy no funcione por lo que hay que instalar los paquetes a mano yay -S libpng12 ncurses5-compat-libs fxload gtk2

yay se queja de las claves pgp es posible que sera por que resolv.conf tiene q estar explicitamente relleno, es decir, nameserver 8.8.8.8 nameserver 8.8.4.4

Importante sin Digilent USB-JTAG Drivers

To use Digilent Adept USB-JTAG adapters (e.g. the onboard JTAG adapter on the ZedBoard) from Vivado, you need to install the Digilent Adept Runtime.

Make sure you have installed fxloadAUR from the Arch User Repository .

To install the Digilent Adept Runtime, install digilent.adept.runtime Arch User Repository and digilent.adept.utilities. Linux cable driver $ cd {vivado_install_dir}/data/xicom/cable_drivers/lin64/install_script/install_drivers Then run as root privilege: $ sudo ./install_drivers

Instalacion de los drivers

/opt/Xilinx/Vivado/2019.2/data/xicom/cable_drivers/lin64/install_script/install_drivers

Instalacion de las tarjetas digilent

https://reference.digilentinc.com/vivado/installing-vivado/v2019.2

Paquetes Archlinux interesantes

https://aur.archlinux.org/packages/digilent-vivado-scripts-git/

Links

https://wiki.archlinux.org/index.php/Xilinx_Vivado

jmgomez-IAA commented 4 years ago

GRMON

Instalacion

Prerequisitos

sudo pacman -S libusb libusb-compat sudo pacman -S libftdi libftdi-compat-0.20-7

Ejecutable

wget https://www.gaisler.com/anonftp/grmon/grmon-eval-64-3.2.2.tar.gz --2020-04-21 13:32:46-- https://www.gaisler.com/anonftp/grmon/grmon-eval-64-3.2.2.tar.gz tar xvf grmon-eval-64-3.2.2.tar.gz

Ejemplo de uso:

sudo /home/jmgomez/Workspace/fpga/grmon-eval-3.2.2/linux/bin64/grmon -u -uart /dev/ttyUSB1 -baud 230400 GRMON debug monitor v3.2.2 64-bit eval version

using port /dev/ttyUSB1 @ 115200 baud GRLIB build version: 4246 Detected frequency: 74.0 MHz

Component Vendor LEON3 SPARC V8 Processor Cobham Gaisler AHB Debug UART Cobham Gaisler AHB/APB Bridge Cobham Gaisler LEON3 Debug Support Unit Cobham Gaisler LEON2 Memory Controller European Space Agency SPI Memory Controller Cobham Gaisler Generic UART Cobham Gaisler Multi-processor Interrupt Ctrl. Cobham Gaisler Modular Timer Unit Cobham Gaisler

Use command 'info sys' to print a detailed report of attached cores

grmon3> info sys

cpu0 Cobham Gaisler LEON3 SPARC V8 Processor
AHB Master 0 ahbuart0 Cobham Gaisler AHB Debug UART
AHB Master 1 APB: 80000700 - 80000800 Baudrate 115200, AHB frequency 74.00 MHz apbmst0 Cobham Gaisler AHB/APB Bridge
AHB: 80000000 - 80100000 dsu0 Cobham Gaisler LEON3 Debug Support Unit
AHB: 90000000 - a0000000 AHB trace: 128 lines, 32-bit bus CPU0: win 8, itrace 128, V8 mul/div, lddel 1 stack pointer 0x4007fff0 icache 2 8 kB, 16 B/line dcache 2 4 kB, 16 B/line mctrl0 European Space Agency LEON2 Memory Controller
AHB: 40000000 - 80000000 APB: 80000000 - 80000100 8-bit static ram: 1 512 kbyte @ 0x40000000 spim0 Cobham Gaisler SPI Memory Controller
AHB: fff70000 - fff70100 AHB: 00000000 - 00400000 IRQ: 7 SPI memory device read command: 0x0b uart0 Cobham Gaisler Generic UART
APB: 80000100 - 80000200 IRQ: 2 Baudrate 38381, FIFO debug mode available irqmp0 Cobham Gaisler Multi-processor Interrupt Ctrl.
APB: 80000200 - 80000300 gptimer0 Cobham Gaisler Modular Timer Unit
APB: 80000300 - 80000400 IRQ: 8 8-bit scalar, 2 32-bit timers, divisor 74

grmon3>

jmgomez-IAA commented 4 years ago

Arty 7

Esta FPGA si incluye salidas para alta velocidad, Seccion 10.2. Incluye dos conector pmod headers para conectar alta velocidad rutadas a diff 100 (Seccion 10).

https://reference.digilentinc.com/_media/reference/programmable-logic/arty/arty_rm.pdf?_ga=2.228559517.1644040385.1587807559-1631419904.1587460596

no obstante en este foro hablan mas del tema: https://forum.digilentinc.com/topic/3626-arty-io-max-switching-speed-of-the-signals/#comment-13643

Differential PMOD Challenge

How fast can YOU transmit and receive 1048576 32-bit words though 12 inches of cable without an error using only 4 differential wire pairs? Link

jmgomez-IAA commented 4 years ago

Bibliografia

Series 7 User Manual

jmgomez-IAA commented 4 years ago

Artix 7

Q&A LVDS and 2.5V remember there were issues on Artix with 2.5 V LVDS mode for inputs if the bank voltage is not 2.5 V (you can use e.g. 1.8 V single-ended inputs on a 3.3 V powered bank, but I think not LVDS). Maybe someone else recalls the details.