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jmgomez-IAA / pyGRMON

Usage of the UART master of the GR718B
GNU General Public License v2.0
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Create a test using SIST port #1

Open jmgomez-IAA opened 4 years ago

jmgomez-IAA commented 4 years ago

SpaceWire In-System Test

Description

SIST port is port 19 of GR718B. The SIST allows direct access to the switch matrix of the router

The SIST module is connected to SpaceWire router via an internal FIFO port. The other side of the SIST module is connected to the AMBA APB bus, and can be controlled through the UART and JTAG interfaces.

Registers

SpaceWire In-System Test registers described in section 7.3 of GR718B Data sheet and user manual.

Register name Register acronym AMBA address
SpaceWire Address Register 0-7 SIST.ADDR[0-7] 0xFFE00200 - 0xFFE0021C
Protocol ID and Polynomial Register SIST.PID 0xFFE00220
Seed Register SIST.SEED 0xFFE00224
Packet Length Register SIST.LEN 0xFFE00228
Control Register SIST.CTRL 0xFFE0022C
Error Register 0 SIST.ERROR0 0xFFE00230
Error Register 1 SIST.ERROR1 0xFFE00234
Error Register 2 SIST.ERROR2 0xFFE00238
Packet Counter Register SIST.PKTCNTR 0xFFE0023C
Timer Register 0 SIST.TIMER0 0xFFE00240
Timer Register 1 SIST.TIMER1 0xFFE00244
Status Register SIST.STAT 0xFFE00248
State Register SIST.STATE 0xFFE0024C
Transmitter Byte Count Register SIST.TXBYTECNTR 0xFFE00250
Receiver Byte Count Register SIST.RXBYTECNTR 0xFFE00254
Time-Code Register SIST.TIME 0xFFE00258
Protection Register SIST.PROT 0xFFE0025C
Data Input Registers 0 - 7 SIST.DIN[0-7] 0xFFE00280 - 0xFFE0029C
Data Output Registers 0 - 7 SIST.DOUT[0-7] 0xFFE002A0 - 0xFFE002BC

SpaceWire Packet

Packet transmited to port 1.

Byte SpwPacket Register Values Notes
0 Path0 Address SIST.ADDR[0] 0x0 First byte of the address path
1 Logical Address SIST.ADDR[0] 0x1 Target node address 0xFE default
2 Potrocol ID SIST.PID 0x0 Chunk SpaceWire Packet
3 Transaction Id SIST.SEED 0x1 Transaction identifier, is the seed of the packet
4-6 Data Length SIST.LEN 0xF length of the data
7 Header CRC --- --- Autocalculated Hedaer CRC from Logial Address inclusive
8 - (8+Data Length) Data pseudo random data generated from seed
(8+Data Length + 1) Data CRC CRC of the data

Configuration

Register Address Reset Value Notes
SIST.PROT 0xFFE0025C 0x55AA0001 Enable SIST
RTR.PCTRL 0xFFF2084C 00108420 0x000000C4 Enable SIST port19, Clear FIFOs and Enable cfgPort
RTR.PCTRL2 0xFFF209CC 0x00000000 Enable SIST
SIST.ADDR0 0xFFE00200 0x01000000 Forward to port 1
SIST.PID 0xFFE00220 0x002D00F0 Protocol identfier 0xF0
SIST.SEED 0xFFE00224 0x00010001 Transaction id = 1
SIST.LEN 0xFFE00228 0x0000000F Packet Data Length 16 bytes
SIST.TIMER0 0xFFE00240 0x00000000 Counts the transmission time
SIST.TIMER1 0xFFE00244 0x00000000 Counts the transmission time
SIST.CTRL 0xFFE0022C 0x81090001 Start TX, Addr len 1, seqlen 1, rate 1

Verfication

Register Address Notes
SIST.TXBYTECNTR 0xFFE00250 Bytes remainning to transmit
RTR.PSTS 0xFFF208CC Bytes remainning to transmit
jmgomez-IAA commented 4 years ago

Es necesario activar el sist Port en el system level test configuration, cfg 2 register bit en.

jmgomez-IAA commented 4 years ago

Las address del sist, van en orden inverso. Es decir, el registro addr2 incluye las direcciones que se usan antes que el registro addr1. Dentro del registro, primero se usan las address 7-0, 15-8, 23-16, 31-24. Es lógico, pues la dirección lógica del dispositivo es el byte 31-24 del addr0.