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jnk0le / cortexm-AES

high performance AES implementations optimized for cortex-m microcontrollers
MIT License
40 stars 4 forks source link

4 byte alignment required due to ldm/stm #5

Open jnk0le opened 2 years ago

jnk0le commented 2 years ago

ctx, input and output data need to be 4 byte aligned to not crash

cm0 will crash even with unaligned ldr cm7 prefers 8 byte alignment for perf reasons