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joefutrelle / tinycube

AVR ATtiny85-based temperature logger
Creative Commons Zero v1.0 Universal
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reset on sleep #17

Open joefutrelle opened 9 years ago

joefutrelle commented 9 years ago

The device sometimes resets on sleep causing it to restart logging from the beginning of the eeprom (need to confirm).

This may be related to a low power condition as I'm seeing surprisingly low battery life on 3x AAA batteries. The battery hog is almost certainly the LED display.

Running out of power also seems to cause incorrect RTC readings and gibberish on the display.

joefutrelle commented 9 years ago

Need a debug display that shows when the device resets.

joefutrelle commented 9 years ago

That debug has interesting behavior which is that it doesn't show up initially -- something is not letting it drive the debug display. Then, upon first sleep, there's a reset.

Subsequently everything runs normally. I have observed what looks like a reset on every sleep, or sporadically, but I can't reliably reproduce that. I just swapped out the eeprom chip and can swap out the MCU if I see intermittency again.

joefutrelle commented 9 years ago

Aha, so this post

https://www.insidegadgets.com/2011/02/05/reduce-attiny-power-consumption-by-sleeping-with-the-watchdog-timer/#comment-30270

says that the WDT will reset if the WDT ISR fires while the device is awake, which was happening in debug mode because the long display cycle was exceeding the duration of a WDT interrupt cycle. Now, I don't know why it's still happening when I've got that entire display cycle disabled, but it may be that the flag described in this post will address that issue.

joefutrelle commented 9 years ago

It doesn't. In debug mode, I'm seeing correct behavior--the device logs multiple data points and doesn't reset.

With debugging off, I only get one data point which means the device is getting reset.

joefutrelle commented 9 years ago

The relevant section of the datasheet:

• Bit 6 – WDIE: Watchdog Timeout Interrupt Enable When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set, the Watchdog Time-out Interrupt is enabled. In this mode the corresponding interrupt is executed instead of a reset if a timeout in the Watchdog Timer occurs. If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is cleared, the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after each interrupt.

joefutrelle commented 9 years ago

I think that is actually a red herring. Scrutinizing power.c I noticed that I'm not delaying before power down, and once I added a slight delay before power down I stopped getting spurious resets, which I was seeing even with debugging. Here's a nice run (date/time is not exactly right)

2014-11-08T17:44:08 24.75C
2014-11-08T17:44:16 24.50C
2014-11-08T17:44:25 24.25C
2014-11-08T17:44:34 24.25C
2014-11-08T17:44:42 24.00C
2014-11-08T17:44:51 24.00C
2014-11-08T17:44:59 24.00C
2014-11-08T17:45:08 24.00C
2014-11-08T17:45:17 23.75C
2014-11-08T17:45:25 23.75C
2014-11-08T17:45:34 23.75C
2014-11-08T17:45:43 23.75C
joefutrelle commented 9 years ago

Just got a clean run with debugging off by putting long pauses around powered-up code. Will now attempt with debugging display completely unplugged from the device.

joefutrelle commented 9 years ago

Not clean. The RTC LED behaved like it was resetting and EEPROM data confirms.

2014-11-08T18:11:36 24.00C
2014-11-08T18:11:45 24.00C
2000-00-00T00:00:00 0.00C
2014-11-08T18:11:19 24.00C
2000-00-00T00:00:00 0.00C

Weird timing interactions are underneath this; very difficult to debug.