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josecm / riscv-hyp-tests

A bare-metal application to test specific features of the risc-v hypervisor extension
GNU General Public License v3.0
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Fix incorrect condition for 'vs access to time succeeds' test #11

Closed autley closed 1 year ago

autley commented 1 year ago

The test for 'VS-mode access to time succeeds with mcounteren.tm and hcounteren.tm set' should PASS when no exception is triggered. It was previously checking for a virtual instruction exception and FAILING on the correct behavior (no exception).

on-behalf-of: @ventanamicro autley@ventanamicro.com

autley commented 1 year ago

It looks like this test case passes on spike (1.0.1-dev). But the test condition doesn't match the testcase description, and I don't believe throwing the illegal instruction exception is the architecturally correct behavior.

josecm commented 1 year ago

@autley Just a small correction: the test was checking for an illegal instruction exception, not a virtual instruction exception. Nevertheless, I agree with your overall assessment. However, this seems to be heavily implementation-defined. The spec states that "Implementations can convert reads of the time and timeh CSRs into loads to the memory mapped mtime register, or emulate this functionality in M-mode software.". This is probably the case for spike, so the test should probably allow for both implementations, i.e., either there is no exception or it is an illegal instruction exception.