r0.1 errata

[joshajohnson]

This issue will document any errata / areas for improvement for future versions.

Note: HyperRAM and SD card are yet to be validated, issues list may grow once they are brought up.

Errata:

• [X] ECP5 ball T12 has a GND via partially occluding the pad
• [X] JTAG labels cannot be seen if header is installed
• [X] Diff pairs laid out uniquely, +/- is flipped compared other boards + uses C/D pair which lack differential pair drivers. 0:4 (PMOD 1:7) = A:B etc is ideal, C:D okay as backup.

Improvements:

• [X] Move HyperRAM to 1v8 for increased speed, will require a dedicated bank / power supply
• [X] BOM optimisation / consolidation, particularly with caps and voltage feedback network
  • [X] Move usb_pu to bottom side with rest of 1k5 resistors
  • [X] 1v1 regulator appears to work fine with 2 x 10uF caps, does not require 22uF
  • [X] USB input cap can be commonised
  • [X] LED resistors to 1k5 - reduces BOM along with being a better brightness
  • [X] Standardise on 0402 components where possible
  • [X] Move DC:DC to smaller SOT package
  • [X] All LED drivers to bottom of board, confirm CDONE requires FET?
• [X] Move status LED vias away from the edge to aide with panelisation
• [X] Add USB pads under USB connector for easy flashing
• [X] Move as many vias up to 0.2/ 0.50mm as possible, or 0.2/0.45 under BGA
• [X] Change button as KMR2 is a bit hard to press

TODO:

• [ ] Validate HyperRAM and SD card on r0.1 before ordering r0.2.
• [X] Update PMOD breakout to use ports B,C,F,G.
• [X] Update DFU bootloader with latest pinout.
• [X] Update .pcf and change makefile so examples work on both boards.

[joshajohnson]

Expanding on the pinout errata, there are two main areas for improvement. Please note I'm not an ECP5 expert (far from it!) so there may be some inaccuracies in the below.

Diff pair pinout is not compatible with the de-facto PMOD standard.

The de-facto standard for diff pairs over a PMOD connector is +/- on 1/7, 2/8 etc. example Ports A -> D on the ECP5 Mini have the diff pairs the other way around, so may cause issues. If you are designing the ECP5 Mini into a custom board, or using single ended IO, this is not a problem.

C/D Pairs are used for IO on Left and Right Sides

Per the lattice IO Guide (pages 6, 10), there are up to two sets of diff pairs per IO block on the left and right sides of the ECP5. The A/B pair contain true LVDS drivers, whereas the C/D pair do not. If possible we should break out A/B pairs instead of C/D pairs, as they have greater functionality. Note the top / bottom sides do not have LVDS drivers on any pins, so we should aim to have dedicated PMODs with the LVDS pairs run to them, leaving other PMODSs with the lesser featured IO. If you are not taking advantage of the LVDS drivers, this is not a problem.

[giggiu16]

Hi @joshajohnson! When do you think the rev 0.2 will be finished? I really would like to try to assemble the board, as my first BGA assembly test 😃.

Thank you for your good work!

[joshajohnson]

Hey @giggiu16!

I'm hoping to finish layout in the next day or two, but I won't have time to assemble / validate the changes / update the constraints file etc for a few months (I'm not guaranteeing anything before March - April, but I'll do my best to get around to it earlier).

In saying this, all of the IO changes are low risk as they are just changing the pinouts, and aside from the hyperram moving to 1v8 there were not too many changes to the core of the board, so should be fairly low risk.

I'll ping you here once it's done so you can kick off the assembly :)

[giggiu16]

Thank you @joshajohnson and thank you again for your good work. I will try my best to assemble the r0.2 and test out the other untested things :)

[joshajohnson]

Hey @giggiu16, 0.2 should be ready to order, files are in hardware/0.2/outputs. I've just ordered mine to fingers crossed they work...

Feel free to fire away with any questions / issues / PRs etc, interested to hear how you go!