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jotego / jt12

FM sound source written in Verilog, fully compatible with YM2612, YM3438 (JT12), YM2203 (JT03) and YM2610 (JT10)
GNU General Public License v3.0
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Registers part fix for jt10 #37

Closed furrtek closed 4 years ago

furrtek commented 5 years ago

Some registers didn't have part checks for writes, this was messing up the timer A (part 0) and some ADPCM-B (part 1) register values.

Also, IRQ enables for timers were swapped in jt12_top.

jotego commented 5 years ago

Thanks a lot for the patch. I have not applied it directly because I think all the control registers should be affected by the !part condition. Please have a look at this commit I made based on your patch.

furrtek commented 5 years ago

Confirming that it works just as well :)

jotego commented 5 years ago

Great! I still have to check I didn’t break anything on the Megadrive but I think it should be ok.

Notice that I have left the separated output signals. If you don’t need them you can leave them unconnected in the instance. If you call the name but leave empty the assignment in the brackets you won’t get any warning. Like this

Jt10 myjt10( .unused( ), // other stuff );

El El lun, 10 jun 2019 a las 10:08, Furrtek notifications@github.com escribió:

Confirming that it works just as well :)

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jotego commented 5 years ago

Could you leave the separated output pins in jt12_top intact? They are used in other instantiations. For instance, they are used in the ZX Spectrum core of MiSTer (for recreating a real-life add-on with two YM2203) for instance.

I think the rest of the corrections are fine. If you reverse jt12_top I can do the merge.

furrtek commented 5 years ago

Didn't meant to update the file here, sorry. I'm still confused about some things with git, I'll restore jt12_top to your version with the separated outputs.

jotego commented 4 years ago

We left this thread open. Closing it!