jotego / jtcores

FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket

https://patreon.com/jotego

GNU General Public License v3.0

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Closed jotego closed 8 months ago

jotego commented 1 year ago

Such as done in ce668848 for jtbubl, take out the cen gating operation to mem.yaml and make it global to all CPUs.

skip systems of type main/sound CPU with latch-only communication (not relevant)
remove all RECOVERY operations from the core, or it may create instability

Cores

jotego commented 9 months ago

outrun/shanon

The M68k cpu_cen/cpu_cenb can be made from a 20MHz cen from mem.yaml:

always @(posedge clk) begin
    cpu_cen  <= cen20 &  cen10;
    cpu_cenb <= cen20 & ~cen10;
end

But using a 48MHz base clock gated by two M68k CPUs which access both ROM and RAM from SDRAM results in a max frequency about 15MHz.

It is probably not worth it to retro fit the old cores with this novelty.