Convert CPS cores to mem.yaml format

[jotego]

These cores need new features added to mem.yaml as they have a more sophisticated use of the SDRAM. Hence, I am taking them out of #480 and giving them their own issue

• [x] Bank decided upon the offset table at the header
• [ ] 64MB SDRAM suppor on mem.yaml
• [ ] Data LATCH used on MiST/SiDi (support on mem.yaml)
• [ ] cps1
• [ ] cps15
• [ ] cps2

[jotego]

CPS cores present a highly customized ROM download:

• bank starts are not fixed, but stored in the ROM header
• the sound CPU data is written at an offset in the same bank as the main CPU. The starting address for applying this offset is derived from the header
• CPS1 does not use bank 1
• Pang3 CPU data must be decripted, a header bit enables it

Actions:

• jtframe_dwnld: derive active bank from header (partially executed in 7637bb0)
• jtframe tool must enable the header data parsing for jtframe mem, see cps1/cfg/xmem.yaml for a syntax proposal
• jtframe load of config files must be made less command-specific, so jtframe-mem can load the header configuration from the TOML easily
• for CPS1/CPS1.5 move sound CPU data to bank 1, to avoid the variable offset approach

[jotego]

Look at #561 after completing this one

[jotego]

jtframe can load data into banks derived from the header (completed in 6091599e)

Pending tasks:

• [ ] for CPS1/CPS1.5 move sound CPU data to bank 1, to avoid the variable offset approach