s18: try different length for HS/VS signals

[jotego]

Some monitors are troubled with JTS18 analogue video output. Try this:

• [x] Check that HS length is like the original (VS already checked). The original screenshot is in the doc folder.
• [x] Compile the core for longer HS lengths and make the file available here for users to check

[jotego]

You could associate the length to the debug_bus, so users can try a few manually

[PapiFed]

Just FYI using DV I have: No sync on a Sony PVM-2950 Sync on a JVC TMH-150cg

[rp-jt]

I have compiled the core for varying manually the length of HS and VS You can find the rbf file here:

jts18.rbf.zip

To do so, please press the keys [+] or [-] (or equivalent to where they are in the Spanish keyboard) to adjust horizontally and "Shift + [+]" or "Shift + [-]" to adjust vertically. I leave the position of the keys in the Spanish keyboard below for reference.

To go back to the original settings, Press either "Ctrl + [+]" or "Ctrl + [-]"

An eight-digit number should come up in the bottom of the screen when doing so. The four digits on the right are associated with HS and the 4 in the left with VS. Please let us know if there's an eight digit combination that works for you. Thanks

[Schermobianco]

My test on PVM Panasonic BT-1415DA

https://streamable.com/g5cjcy

[PapiFed]

Are Sync width and sync length the same thing ?

[jotego]

Are Sync width and sync length the same thing ?

Yes. The important parameters are the synchronization signal frequency and its active time (expressed as pulse width or length)

[PapiFed]

Are Sync width and sync length the same thing ?

Yes. The important parameters are the synchronization signal frequency and its active time (expressed as pulse width or length)

Having the option to modulate the vertical sync width in all Cores would be a dream for all high end Ikegami monitors owners (probably JVC DT-V owners also). It is currently only available in a few Cores.

[PapiFed]

Played around quite a bit with this test Core but could not get any non-scrambled image to display on the 2950.

[Fpg-Lee]

Played around quite a bit with this test Core but could not get any non-scrambled image to display on the 2950.

Same here, implementation would benefit from H+V adjustments within the visible GUI via HDMI to stabilize CRT syncs. P.s the controls wouldn't respond after config for me, I couldn't get a coin to insert to further test game inputs on either game.

[Fpg-Lee]

'Dirty' S18 core control pads don't respond after before/after config for me, I couldn't get a coin to insert to further test game inputs on either game. Thanks

[deepthaw]

FYI ] and / are the US Keyboard equivalents of + and -

[deepthaw]

Went through all 255 possibilities (I assume only the top octet should change?) and did not find anything that synced. Values ending in 2 seemed to be the closest, with no rolling but still clearly off. Sony KV35V75 running svideo.

[Fpg-Lee]

FYI ] and / are the US Keyboard equivalents of + and /

Thanks. Have you tried the core via HDMI? the Core will not add coins, the BETA does.

[deepthaw]

FYI ] and / are the US Keyboard equivalents of + and /

Thanks. Have you tried the core via HDMI? the Core will not add coins, the BETA does.

I did but I didn't even try to insert coins. I spent the whole time stepping through the sync values.

[terminator2k2]

FYI ] and / are the US Keyboard equivalents of + and /

Thanks. Have you tried the core via HDMI? the Core will not add coins, the BETA does.

I did but I didn't even try to insert coins. I spent the whole time stepping through the sync values.

its likely a debug core , made with no inputs/sound

[jotego]

So far three users tried this debug build and it only helped one (@Schermobianco). @Schermobianco's video is not available anymore but I think the result was that going from a zero to a non-zero value made it visible. I measured the PCB and found that HS was 6% longer there (equivalent to 2 pixels). I have modified the core to match the PCB length (b7015c27). The extra 320ns may help some users but from the reports here it looks like this change will benefit few people.

HS signal measured on the board: 5.32us active time length

[Schermobianco]

Hi @jotego , no it doesn't help me the better sync I had was the same as the original core (top left sync issue)

[Fpg-Lee]

Hi @jotego , no it doesn't help me the better sync I had was the same as the original core (top left sync issue)

Is the updated Core compiled and available? Thanks.

[Schermobianco]

Hi @jotego , no it doesn't help me the better sync I had was the same as the original core (top left sync issue)

Is the updated Core compiled and available? Thanks.

My photo is from the test core, the updated core compiled isn't available right now

[Fpg-Lee]

Hi @jotego , no it doesn't help me the better sync I had was the same as the original core (top left sync issue)

Is the updated Core compiled and available? Thanks.

My photo is from the test core, the updated core compiled isn't available right now

Gotcha, I ran the updater incase Jose added it to Update all, I got my fingers crossed it improves CRT sync compatibility for many CRT users.

[bazset]

I tried the first custom core posted. I tried every combination available but nothing synced the picture (Sony PVM).

@jotego when will the new core be posted? will it be combined into the update_all core or will it need to be manually downloaded?

[jotego]

@jotego when will the new core be posted? will it be combined into the update_all core or will it need to be manually downloaded?

jts18_8db7b95.zip

This version has exactly the same HS/VS signals as the original board. Let me know if it works.

[Schermobianco]

@jotego when will the new core be posted? will it be combined into the update_all core or will it need to be manually downloaded?

jts18_8db7b95.zip

This version has exactly the same HS/VS signals as the original board. Let me know if it works.

@jotego Same here

https://github.com/jotego/jtcores/assets/89546473/009137fc-dadd-40da-9f73-c4aefa6490c8

[jotego]

Thanks for testing it. We will build another debug version just focusing on HS as it looks like the vertical signal gets locked correctly.

[bazset]

@jotego I tried the new core in jts18_8db7b95.zip and this is what i got. same as the original core.

https://github.com/jotego/jtcores/assets/78243398/36ff76a6-3374-46ae-9736-a188a9c5b79d

[rogersouza-work]

@jotego I tried the new core in jts18_8db7b95.zip and this is what i got. same as the original core.

sd.mp4

I've got the same image on my arcade (Toshiba tri-sync monitor)

[danieldoyle]

@jotego I tried the new core in jts18_8db7b95.zip and this is what i got. same as the original core. sd.mp4

I've got the same image on my arcade (Toshiba tri-sync monitor)

Which model? Most arcade monitors have hfreq/hhold adjustments that will solve it

[rogersouza-work]

@jotego I tried the new core in jts18_8db7b95.zip and this is what i got. same as the original core. sd.mp4

I've got the same image on my arcade (Toshiba tri-sync monitor)

Which model? Most arcade monitors have hfreq/hhold adjustments that will solve it

That's not the problem. I've got some arcade PCBs, Mister Fpga, Raspberry Pi and It only happens with this core.

[rogersouza-work]

@jotego I tried the new core in jts18_8db7b95.zip and this is what i got. same as the original core. sd.mp4

I've got the same image on my arcade (Toshiba tri-sync monitor)

Which model? Most arcade monitors have hfreq/hhold adjustments that will solve it

My chassis/monitor is a Toshiba PF D29C051

[jotego]

Thank you for all the feedback.

The monitor model is actually important. This does not happen to everyone. It does not happen on any of the screens we can test it. The core has the same video signals as the original board, so I would assume that most arcade monitors should work well with it. We'll check if we can buy one of these screens for an affordable price as I am always up for making the analog video output more compatible.

In the meantime, as I said above, we will prepare another debug core allowing other settings and upload it here.

[bazset]

my monitor is a Sony PVM-1953MD

[Schermobianco]

PVM Panasonic BT-S1415DA

[Fpg-Lee]

My consumer CRT= iLO DTV2794

[jotego]

We are looking into adding more advance HS/VS customization options in the OSD menu, but it will still not be enough for all monitors and cores. Some monitors just not lock certain frequencies in time to display the active video part of the signal.

I think replacing the capacitors on these monitors may have a chance of improving the PLL performance. Particularly, around the supply decoupling and the horizontal synchronization circuit. Please consider servicing your monitors.

[rogersouza-work]

I have a System 18 Shadow Dancer original PCB and I have no problems with sync in both Egret 3 or Sega Blast City. I am sorry but I can not agree with your argument. Lots of people are having sync problems ONLY with this core. How can this be a recap problem?

[jotego]

The core produces the same frequency and width for all the sync pulses. But there is one difference I cannot control from the core: the voltage. That will also have an effect on the PVM PLL. The board does not have the same lov/high level voltages as a MiSTer FPGA. These voltage levels are fixed and cannot be modified by the core.

Replacing the capacitors may help because PLL's have a low-pass filter in the loop that will be dominated by some capacitor, which might be discrete in these monitors. Reducing supply noise will also help in having the PLL lock up more quickly.

Lots of people are having sync problems

I only count the users in this thread. Even if only a few users, we have been searching for the PVM models that fail to buy one. We have not found one yet. Our test equipment works correctly with this core and we cannot reproduce the issue.

The only thing we can do is give a finer control on the sync signals to the user and let you play with different combinations until one works. Another possibility is to enable a higher sync rate (closer to 60Hz), which should help too at the cost of increasing game speed. I am not a big fan of this second option.

[jotego]

The blue line is an original SYSTEM 18 PCB, the yellow one is the core on a SiDi128. As you see the voltage levels are different but the frequency and width are equal. Everyone, how do you produce the video signal? Is it direct video (HDMI to VGA converter), the old analog IO board or the new digital IO board?

[rogersouza-work]

The blue line is an original SYSTEM 18 PCB, the yellow one is the core on a SiDi128. As you see the voltage levels are different but the frequency and width are equal. Everyone, how do you produce the video signal? Is it direct video (HDMI to VGA converter), the old analog IO board or the new digital IO board?

I am using an analogue I/O board with Antonio's Villena Jamma Adapter. Anyway, I am having the same sync problem using analogue I/O straight on the JVC TM-H1750CG

[rogersouza-work]

The blue line is an original SYSTEM 18 PCB, the yellow one is the core on a SiDi128. As you see the voltage levels are different but the frequency and width are equal. Everyone, how do you produce the video signal? Is it direct video (HDMI to VGA converter), the old analog IO board or the new digital IO board?

I am using an analogue I/O board with Antonio's Villena Jamma Adapter. Anyway, I am having the same sync problem using analogue I/O straight on the JVC TM-H1750CG

[danieldoyle]

For anyone on this thread feeling really confident caps don’t play a role in sync:

https://youtu.be/oMQq2As55Ho?si=ltAViKN2PGNzR7bj

just to clarify what’s happening in the video if it isn’t obvious:

1. No sync on cold start
2. Caps get toasty gradual sync happens
3. Full synched, power off and on and out of sync
4. Repeat this a number of times and the window of time decreases as the caps are already warmed up

Then wait a few minutes and we get back to cold start state. Mister can be left on of course. So yeah this TV happens to be right on the edge so it’s a good demo of why caps matter.

[bazset]

I am using the VGA out on a MiSTer Mini-ITX Ironclad Plus board.

[jotego]

For anyone on this thread feeling really confident caps don’t play a role in sync:

https://youtu.be/oMQq2As55Ho?si=ltAViKN2PGNzR7bj

This is a very good example. Thank you.

[HawkeyeRetro]

Jotego asked me to share my sync issue in this thread.

I have a 6.0 I/O board and have noticed issues with sync for the TMNT, Simpsons, and Splatter House cores. I have no other sync issues with any other cores for arcades or consoles.

My output is via component cables. I have tried these cores on two different monitors with the exact same result. One is a Toshiba A model (consumer CRT) the other is a Sony PVM 14m4u.

I find it perplexing that the sync issue manifests exactly the same on two different monitors. Thanks!

https://github.com/jotego/jtcores/assets/172640919/a185afdf-8ca3-4a5c-908d-d41404308038

https://github.com/jotego/jtcores/assets/172640919/020b64f2-5ec3-4b0d-9dad-6b04ac966997

[PapiFed]

Using Direct Video through an HDFury3 Syncs on a JVC TM-H150cg with a clone input card. No sync on a Sony PVM-2950

[PapiFed]

For anyone on this thread feeling really confident caps don’t play a role in sync:

https://youtu.be/oMQq2As55Ho?si=ltAViKN2PGNzR7bj

just to clarify what’s happening in the video if it isn’t obvious:

1. No sync on cold start
2. Caps get toasty gradual sync happens
3. Full synched, power off and on and out of sync
4. Repeat this a number of times and the window of time decreases as the caps are already warmed up

Then wait a few minutes and we get back to cold start state. Mister can be left on of course. So yeah this TV happens to be right on the edge so it’s a good demo of why caps matter.

How do you know it is the caps and not the flyback ?

[jotego]

How do you know it is the caps and not the flyback ?

The flyback generates high voltage to drive the tube. It is not related to sync signal processing. Having said that, if the caps in the flyback are degraded, it will generate more switching noise. This noise may couple into the PLL supply and affect the PLL lock performance. That's why replacing decoupling caps may also help.

[rogersouza-work]

https://github.com/jotego/jtcores/assets/169895421/b387395d-b225-473e-a45c-c8f8697c8f9e

[terminator2k2]

i use direct video and have no problems when used with my Sony consumer crt tv

[jotego]

Let's try a shorter HS than the original. This compilation uses 3us for HS width, which is a more typical value. Let me know how it goes.

jts18_6ae69c20.rbf.zip

[Schermobianco]

Let's try a shorter HS than the original. This compilation uses 3us for HS width, which is a more typical value. Let me know how it goes.

jts18_6ae69c20.rbf.zip

JT in my case it's worse