jotego / jtcores

FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket
https://patreon.com/jotego
GNU General Public License v3.0
236 stars 41 forks source link

shouse: flip not working #767

Open Toryalai1 opened 2 months ago

Toryalai1 commented 2 months ago

When launching splatterhouse on the analogue pocket and mister (fresh SD card), the game loads upside down. The Rotate Screen option in the OSD doesn't work. When I go into Service mode and toggle the flip option, it does flip, but when exiting, it goes back into upside down.
Also, when you toggle the "Type" option in the Service menu, it also for some reason toggles the flip

Toryalai1 commented 2 months ago

Related ticket: https://github.com/jotego/jtcores/issues/691

gyurco commented 2 months ago

You have to save the NVRAM content to save the flip option inside the service menu. I don't know if it's there on Pocket.

Toryalai1 commented 2 months ago

There is no option to save NVRAM

jotego commented 2 months ago

The same problem occurs in MiSTer. There must be something wrong about the DIP switch definition in the MRA file for that game.

Toryalai1 commented 2 months ago

You are correct, same also in MiSTer

irgun6 commented 1 month ago

Still not working? Tried with an update for the core, but still no flip :(

Exort commented 1 month ago

Interestingly during the loading of the service menu boot during Rom test it does show up in the correct orientation, then flips midway through.

I can confirm that flipping in the service menu does resolve the issue but as there's no way to save it it's not useful.

There's no Flip option in the core menu, at least when this game is loaded, so there's no workaround for this issue.

jotego commented 1 month ago

Implementing the flip hardware in commit 30b45dfb7c0ec52d97741b9a1a3f40ca9148dd4f had the side effect of revealing that horizontal games on Namco System 1 hardware are displayed through a mirror in the cabinet. The default option is to have the screen flip.

Some of them can be flipped in the service menu (like splatter) but in others (like wldcourt) the service menu fails because of a RAM error.

Not a comprehensive table:

Setname Service Menu Can be flipped
faceoff how to control it? Potentially
mmaze
splatter Works Yes
wldcourt Works Yes

Some horizontal games do not appear flipped:

Maybe the best solution will be to provide default values for the NVRAM with games preconfigured with the right flip option.

gyurco commented 1 month ago

I also think the best would be to have a default NVRAM content then. BTW, something's wrong with the Save NVRAM option, as after saving one, I get an EEPROM ERROR during loading. As the core supports scene dumping, I assume the NVRAM content is not (just) the EEPROM, but all memories. Or is it supposed to be correct when building a release, not a dev version?

jotego commented 1 month ago

I just changed it today so in the release builds it will only save the 2kB for the EEPROM. I haven't tested that change, but the old one was loading the data well on the MiSTer this morning. No EEPROM errors.

gyurco commented 1 month ago

Works fine in release mode on SiDi128.

frabico commented 1 month ago

Splatterhouse: Flip is still not working in the new release on Analogue Pocket.

jtmiki commented 1 month ago

I have tested Splatter House with today's compile all and Flip is still not working on Analogue Pocket. Commit: da6cb73

jotego commented 1 month ago

The problem is that jtframe mra is not generating the Saves folder for the Pocket with the EEPROM data.

gyurco commented 1 month ago

Meanwhile I noticed another issue: if the dump is > 2048 bytes, then the 2049th byte is also written to the EERAM, making its content useless (no saved flip setting is used). Here's a signal capture: image

You can see that ioctl_addr=2048 still writes to we0_mx[0], so address 0 is overwritten in the EERAM.

gyurco commented 1 month ago

The cause of the issue is that ioctl_wr asserted at the same time when ioctl_addr is incremented, so sel doesn't have time to de-assert. If it would be in a combinatorial block instead of a sequential, then it would work.

gyurco commented 1 month ago

Simple diff to fix:

diff --git a/modules/jtframe/hdl/ram/jtframe_ioctl_dump.v b/modules/jtframe/hdl/ram/jtframe_ioctl_dump.v
index 5c895565..f037ab52 100644
--- a/modules/jtframe/hdl/ram/jtframe_ioctl_dump.v
+++ b/modules/jtframe/hdl/ram/jtframe_ioctl_dump.v
@@ -125,16 +125,16 @@ assign din3_mx = ioctl_ram ? {DW3==16?2:1{ioctl_dout}} : din3;
 assign din4_mx = ioctl_ram ? {DW4==16?2:1{ioctl_dout}} : din4;
 assign din5_mx = ioctl_ram ? {DW5==16?2:1{ioctl_dout}} : din5;

-always @(posedge clk) begin
-    sel    <= 0;
-    offset <= 0;
+always @(*) begin
+    sel    = 0;
+    offset = 0;
     if( ioctl_ram ) begin
-        if     ( ioctl_addr < OS1 && AW0!=0) begin sel[0] <= 1; offset <= 0; end
-        else if( ioctl_addr < OS2 && AW1!=0) begin sel[1] <= 1; offset <= OS1[23:0]; end
-        else if( ioctl_addr < OS3 && AW2!=0) begin sel[2] <= 1; offset <= OS2[23:0]; end
-        else if( ioctl_addr < OS4 && AW3!=0) begin sel[3] <= 1; offset <= OS3[23:0]; end
-        else if( ioctl_addr < OS5 && AW4!=0) begin sel[4] <= 1; offset <= OS4[23:0]; end
-        else if( ioctl_addr < OS6 && AW5!=0) begin sel[5] <= 1; offset <= OS5[23:0]; end
+        if     ( ioctl_addr < OS1 && AW0!=0) begin sel[0] = 1; offset = 0; end
+        else if( ioctl_addr < OS2 && AW1!=0) begin sel[1] = 1; offset = OS1[23:0]; end
+        else if( ioctl_addr < OS3 && AW2!=0) begin sel[2] = 1; offset = OS2[23:0]; end
+        else if( ioctl_addr < OS4 && AW3!=0) begin sel[3] = 1; offset = OS3[23:0]; end
+        else if( ioctl_addr < OS5 && AW4!=0) begin sel[4] = 1; offset = OS4[23:0]; end
+        else if( ioctl_addr < OS6 && AW5!=0) begin sel[5] = 1; offset = OS5[23:0]; end
     end
 end

I can send a PR if desired.

jotego commented 1 month ago

Would it be ok to delay ioctl_wr by one clock cycle instead in the MiST-related JTFRAME modules? That combinational block is a big large so being able to register it would be good.

gyurco commented 1 month ago

I don't think it's a good idea to put the delay into mist's data_io. If the dump module makes delayed decision, then probably it should delay the appropriate signals itself (just reminds me to delayed cpu_dins at various places, when cpu_din is delayed, but cpu_ok is not...). Using an ioctl_wrl inside jtframe_ioctl_dump could work, but not sure about the mister framework. If it increments address right after wr, then it'll break. Actually the block doesn't use much logic, as most of the contents are static numbers. At least it didn't broke timings in shouse.

jotego commented 1 month ago

Ok. Let's try with the combinational approach for a while. Sometimes logic is faster than I expect.

Could you do the PR so the commit has your name?

gyurco commented 1 month ago

PR sent!