Cores based on the 6144 kHz PLL cause timing errors in MiSTer sys_top

jotego / jtcores

FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket

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Cores based on the 6144 kHz PLL cause timing errors in MiSTer sys_top #794

Closed jotego closed 3 weeks ago

jotego commented 3 weeks ago

Most timing errors seem benign. A lot of them seem to come from signals going through two different clock domains. Some even have synchronizers but are not detected as such by the tool, or maybe you have to be specific about synchronizers in the SDC file.

All cores are tagged as JTFRAME_NOSTA on MiSTer in 58038576. This probably needs a lot of changes in MiSTer's sys_top.

jotego commented 3 weeks ago

Tagged JTFRAME_NOSTA for jtframe_pll6293 cores (s16/outrun/shanon) in 54fb40cf

jotego commented 3 weeks ago

And also jtframe_pll6671 (rastan)

jotego commented 3 weeks ago

SDC constraints were not applied correctly because the pll game was different in each case. Fixed in 8765cd7e