Out Run won't boot

[jotego]

The memory tests pass, but the game won't boot. Once the game halts, it is possible to enter the test mode by pressing F2. Super Hang On boots, but the road is always a straight line and it doesn't get drawn.

• Tried separated access to SDRAM without bus handshaking between main and sub CPUs in be4a810. The memory tests still passed but the game didn't boot. Note that the road RAM doesn't seem to be accesses from the main CPU as it can be blocked in MAME and still works
• Tried disabling RECOVERY in jtframe_dtack
• Tried toggling the road RAM synchronously with the v-int (similar to the PCB) and asynchronously (like MAME)
• Tried not latching the input from the sub to the main CPU:

  always @* begin
  bus_mux  = rom_cs  ? rom_data  :
             ram_cs  ? ram_data  :
             road_cs ? road_dout :
             16'hffff;
  sub_din = bus_mux;
  end

• Tried fixed 1-clock DTACK delay in the mapper
• Tried giving 1 more bit to the main CPU RAM

  always @(*) begin
  xram_addr = { ram_cs, main_addr[15:1] }; // RAM is mapped up
  //if( ram_cs ) xram_addr[15] = 0;
  end

• Tried default settings for the ROM controller about the ok latch

  
  // Main CPU ROM
  .SLOT2_AW   (18),  // 512kB
  .SLOT2_DW   (16),
  //.SLOT2_OKLATCH( 0),
  
  // Sub CPU ROM
  .SLOT3_AW   (18),  // 512kB
  .SLOT3_DW   (16),
  //.SLOT3_OKLATCH( 1),
  .SLOT3_LATCH(0),

• Using a sdram_ok signal like in s16b

      if( ASn && BGACKn )
          sdram_ok <= 0;
      else if( !BUSn || !BGACKn ) begin
          sdram_ok <= rom_cs ? rom_ok : ram_ok;
      end

[jotego]

• If the main CPU can only access the sub RAM, the game still boots in MAME. But, it needs R/W access to the RAM
• Making the mapper reads return always zero does hang the game in MAME
• swapping slots 0 and 1 of bank0 makes no difference

[jotego]

• Tried different clock speeds for the sub CPU
• Tried reading different values when SIO read occurs in sub CPU
• Tried with different mapper read values
• Looked for bus errors in the main CPU
• Verified RAM data reads in main/sub using a separate memory array in simulation
• Tried allowing interrupts one level lower than the right one
• Tried the homebrew memory checker
• Moved SRAM_OFFSET to 22'h20_0000 to prevent overlapping with the main RAM access

[jotego]

Fixed in c40e13e