Open jovanbulck opened 7 months ago
https://lkml.org/lkml/2022/8/30/1520
On platforms with the IA32_XAPIC_DISABLE_STATUS MSR, if SGX or TDX are enabled the LEGACY_XAPIC_DISABLED will be set by the BIOS. If legacy APIC is required, then it SGX and TDX need to be disabled in the BIOS.
Nowadays SGX-Step requires
nox2apic
to operate the APIC timer in memory-mapped I/O mode. It may be useful to also have X2APIC support in SGX-Step.That would require manipulating MSRs instead of MMIO. This is currently not neatly supported in libsgxstep, but if needed one can implement this manually w call gates, eg as follows:
https://github.com/jovanbulck/sgx-step/blob/master/app/apic/irq_entry.S#L44