implements the VU edge case where an integer altering instruction is in the delay slot of a conditional branch and the first instruction following it is another conditional branch based on that integer register.
The original code will take the value of the integer register at that time assuming a pipeline shortcut but that is wrong because having an integer altering instruction directly before a conditional branch on that same integer register causes the pipeline to fail and we need to use the value most recently written to memory.
Can potentially break a lot of games so needs quite a bit of testing.
implements the VU edge case where an integer altering instruction is in the delay slot of a conditional branch and the first instruction following it is another conditional branch based on that integer register. The original code will take the value of the integer register at that time assuming a pipeline shortcut but that is wrong because having an integer altering instruction directly before a conditional branch on that same integer register causes the pipeline to fail and we need to use the value most recently written to memory.
Can potentially break a lot of games so needs quite a bit of testing.