jpiat / arduino

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Receiver Logic Flow #25

Closed Yuejing1992 closed 7 years ago

Yuejing1992 commented 7 years ago

Hi, Would it be possible to provide some description about the receiver side logic flow? Or more comments about those a few lines.

if(edge_val == 0 || edge_val == old_edge_val || (edge_val != old_edge_val && steady_count < 2)) { if( steady_count < (4 SAMPLE_PER_SYMBOL)){ steady_count ++ ; } }else{
new_word = insert_edge(&shift_reg, edge_val, steady_count, &(dist_last_sync), &detected_word); if(dist_last_sync > (8
SAMPLE_PER_SYMBOL)){ // limit dist_last_sync to avoid overflow problems dist_last_sync = 32 ; } //if(new_word >= 0){ steady_count = 0 ; //} } old_edge_val = edge_val ;

From my understanding is like every edge is the half bit of manchester code, i don't understand why need to do so. Then if no change in the edge, we need to insert the edge??