Thank you for your amazing tutorial series. It has been so informative and I have learnt loads!
I'm just having one problem with lesson 09. I'm compiling for my 64-bit Pi 3 (I am not following the tutorial series, only this specific section), and I can not compile the code (I changed the registers to work with 64-bit):
try_lock: mov x1, #0 swp x2, x1, [r0] // stores the value in x1 into the address in x0, and stores the value at the address in x0 into x2 mov x0, x2 blx lr
My error message is "Error: selected processor does not support `swp x2,x1,[x0]'!". Apparently the "swp" instruction was deprecated and removed, and does not exist on later Pi models. Is there a newer, better instruction to accomplish an atomic lock? Or is it my toolchain at fault? I have tried building with -mcpu=cortex-a7 but it tells me it's not a valid CPU, instead suggesting I try cortex-a53, but even then, I get the same error about the instruction not being supported.
Hi all,
I think the deprecated SWP instruction can simply be replaced with the STREX [Store and exchange] instruction which accepts the same parameters.
Thank you for your amazing tutorial series. It has been so informative and I have learnt loads!
I'm just having one problem with lesson 09. I'm compiling for my 64-bit Pi 3 (I am not following the tutorial series, only this specific section), and I can not compile the code (I changed the registers to work with 64-bit):
try_lock: mov x1, #0 swp x2, x1, [r0] // stores the value in x1 into the address in x0, and stores the value at the address in x0 into x2 mov x0, x2 blx lr
My error message is "Error: selected processor does not support `swp x2,x1,[x0]'!". Apparently the "swp" instruction was deprecated and removed, and does not exist on later Pi models. Is there a newer, better instruction to accomplish an atomic lock? Or is it my toolchain at fault? I have tried building with -mcpu=cortex-a7 but it tells me it's not a valid CPU, instead suggesting I try cortex-a53, but even then, I get the same error about the instruction not being supported.