fifo_big implementation in VHDL support library

[jserot]

It seems there's a bug in the implementation of the fifo_big module in lib/vhdl. The FIFO does not notify the full condition even when the it gets full. The problem may be related with condition used for testing this condition (if ( cnt = depth ) can never actually be true, since cnt was declared with a range from 0 to depth -1. Strangely, the problem comes out only with a post synthesis simulation (or with a run on board) and does not show when running behavioral simulation.

The initial problem was reported on Apr 19, 2018 by T. Fanni

[jserot]

This issues actually raised several others related to the fact the code contained in big_fifo.vhd was actually not platform-independant. In particular, it did not generate RAM-based implementations on Xilinx devices (using ISE). After several discussions, it appeared that writing a platform-independant model for a RAM-implemented FIFO was very difficult because it ultimately relies on the actual target hardware and on synthetizer-specific settings. We view it as essential that CAPH essentially remains a platform-agnostic tool, i.e. that it does not rely on hardware and/or vendor specific facilities. As a result, and from version 2.9.0, the official CAPH distribution only contains one FIFO model (that previously named fifo_small.vhd, now renamed fifo.vhd) giving a LE-based implementation on all platforms. Specialized models - and in particular those aiming at inferring RAM-based implementations on specific platforms - should now be provided in a separate repository, named caph-contrib. We are now working on an optimized RAM-based FIFO for Altera devices but we cannot give a release date (our work is focused on the development of the language itself and we do not have time for writing target-specific code..). So, please contribute to CAPH by writing smart, optimized models and tools for your favorite platform and share them on caph-contrib