Closed ryanpatiency closed 5 years ago
@lecopzer, can you clarify?
HI @ryanpatiency
In the comment linked by, it indicate r7 is for sp, but sp is r13 instead. Also quoting from Arm-Cortex-M3 technical reference:
Sorry I don't get the point, "store sp
in r7
" and "sp
is r13
" do not conflict with each other.
"After returning from the ISR, the processor automatically pops the eight registers from the stack. Interrupt return is passed as a data field in the LR, so ISR functions can be normal C/C++ functions, and do not require a veneer."
This talks about how exception return works.
Since PendSV
is not a _normal_ ISR
, it deals with context switch
and never return, we have to handle calling convention ourselves and avoid GCC store any thing at function prologue; otherwise GCC would corrupt our context switch
implementation.
So I wonder if we need naked attribute at all
Could you please disassemble for both function with and without naked
attribute, and explicitly point out anything you thought it's unreasonable?
If you have any question, feel free to ask. Thanks
Hi @lecopzer,
Thanks for your illustration, the concept is clear after I compared the disassembled pendsv
function, the function without naked attribute modify the r7
without restoring it, thus might affect the user program.
Thank you
Answered.
https://github.com/jserv/mini-arm-os/blob/f88e0be74551336bc035fa3a71a2c906b6aadcb5/08-CMSIS/core/src/threads.c#L19
In the comment linked by, it indicate r7 is for sp, but sp is r13 instead. Also quoting from Arm-Cortex-M3 technical reference:
So I wonder if we need naked attribute at all