jstr045329
commented
4 years ago The motivation for doing this is that it can be helpful for testing how well a design holds up in the face of clock jitter.
Open jstr045329 opened 4 years ago
jstr045329
commented
4 years ago The motivation for doing this is that it can be helpful for testing how well a design holds up in the face of clock jitter.
Module should accept: 1) Increment size. 0.1 ns, 2 ns, etc. 2) Vector length 3) Distribution
Resulting time delay vector should look like this: constant timeDelayVec : t_timeDelayVec := ( 0.1 ns, 0.3 ns, 0.7 ns, ... );