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juj / gowin_fpga_code_generators

Interactive code generators for Gowin FPGAs
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How to add new chips? #1

Open tpimh opened 9 months ago

tpimh commented 9 months ago

I have just started exploring GOWIN PLL, and found this tool very useful. I would like to add support for more chips. Where do I start?

In particular, I am now working with GW1NS-UX2CQN48C5/I4, and reading Gowin Clock User Guide.

juj commented 5 months ago

Heya, sorry for the delay, this fell through my queue.

This is a really good question, although given the time I think you probably had your use case covered?

To add new boards, one would register the limits of the board at https://github.com/juj/gowin_fpga_code_generators/blob/e88572f8eaf2436b583f7f6ba7b988907b9eeaa1/pll_calculator.html#L94-L98

I discovered these limits for each board by manually setting ridiculous values into Verilog code via the Gowin IP generator, and then observing the Gowin IDE Synthesis time error messages that resulted.

Then if there are some other discrepancies, those would have to be accounted for, maybe by generalizing the existing code, or similar.

It may be possible that the GW1NS-UX2CQN48C5/I4 board shares the same limits as some other boards, not quite 100% sure. So might only mean adding that one line to boards.

Hope you got going with that board!