Open omus opened 3 months ago
Another example:
Invalid instruction at 0x75fc0a81d157: 0x62, 0xf2, 0x7d, 0x48, 0x7c, 0xc0, 0x62, 0xf1, 0x7d, 0x48, 0xfe, 0x0d, 0x99, 0x40, 0xfe
[1732] signal (4.2): Illegal instruction
I ended up displaying /proc/cpuinfo
in my workflow and found that using GitHub hosted runners for ubuntu-latest
do indeed switch between Intel and AMD CPUs. In my particular case runs were successful on Intel but not AMD. I suspect the cache from main
was original run on Intel.
Yeah we've seen this on 1.9 but I believe it's fixed on 1.10, but haven't confirmed. Seems Julia isn't rejecting caches that were generated on different cpu arches. Is your CI running on different kinds of runners?
Yeah we've seen this on 1.9 but I believe it's fixed on 1.10
Good to know. The reported failures are on Julia 1.9.4
I've had luck setting JULIA_CPU_TARGET
in Docker images so I may try this as a work around for now:
# Set x86_64 targets for improved compatibility
# https://docs.julialang.org/en/v1/devdocs/sysimg/#Specifying-multiple-system-image-targets
env:
JULIA_CPU_TARGET: "generic;sandybridge,-xsaveopt,clone_all;haswell,-rdrnd,base(1)"
I've been seeing some strange behaviors when running Julia code after a successful cache restore. I've been seeing these kinds of failures in multiple workflows at seemingly random locations:
I'm still gathering information on this problem but my going theory is the
vcvtusi2sd
instruction shown from disassembling the hex requires the AVX512F CPU feature and possiblyubuntu-latest
runners may switch between AMD and Intel CPUs?Debugging this has been made more challenging due to #113