Closed TonyReinberger closed 2 years ago
I could be wrong on this. I think it might crash because the designcfg gets out of sync with the HW design. It is missing some of the instances that were placed in the drawing. Maybe from a previous crash. I will update if I learn more or can confirm this.
Kactus2 3.9.171 Windows 64 bit
I have a crash case which should be easy to duplicate because it involves the ipxactexamplelib-master library. It may or may not be related to my earlier crashing problem. I have not progressed back to the hardware design stage since I'm dealing with components that have a large number of ports.
I can not open tut.fi|peripheral.logic|wb_external_mem|1.0
Opening this directly or from the tut.fi|cpu.structure|cpu_example|1.0 HW design causes an immediate crash.
Have you tried generating VHDL on the newest version of Kactus2? The crash regarding opening the tut.fi|peripheral.logic|wb_external_mem|1.0 should be fixed.
I've installed 3.9.333 Windows 64 bit.
Open component still causes immediate crash.
I have not run into the VHDL crash recently. It is very likely a component was corrupted in the early days of trying to learn Kactus2. Perhaps related to other bugs I came across such as deleting bus signals and still having them present in the port map of a component. Still can't open the component in my last comment.
Opening of the component should be fixed in the current version in the repository and it is going to be in the next release version of Kactus2. Meanwhile, you could try manually removing the memory remaps of a component. This should help with the crashes.
Let me know if you experience any further issues with the VHDL generator.
If you have a component placed with no connections and try to generate the VHDL (and probably others) then the program crashes without warning. I'm very new to this program and I'm trying to figure it out but I believe this should be easy to replicate and verify.