I've tested the default value with the latest code, a small lint problem:
port
default setting
generated default
expected default
pad_tdt_dm_core_unavail
1'b0
0
1'b0
When the width is 1 bit, vectorBounds first and second string are empty, thus introducing the problem. Therefore, this case should be specially handled.
After this patch,
port
default setting
generated default
expected default
pad_tdt_dm_core_unavail
1'b0
1'b0
1'b0
The generated verilog code will carry the width information.
I've tested the default value with the latest code, a small lint problem:
When the width is 1 bit,
vectorBounds
first and second string are empty, thus introducing the problem. Therefore, this case should be specially handled.After this patch,
The generated verilog code will carry the width information.
See also: https://github.com/kactus2/kactus2dev/pull/67