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kactus2 / kactus2dev

Kactus2 is a graphical EDA tool based on the IP-XACT standard.
https://research.tuni.fi/system-on-chip/tools/
GNU General Public License v2.0
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[CORRECTIVE] Fix VerilogPortParser find colon problem and ternary operators support #69

Closed vowstar closed 2 years ago

vowstar commented 2 years ago

There are some IPs whose port definitions contain some ternary operators, causing problems in the process of importing verilog.

The main reason is that the original regular expression \\[(.*?)\\s*[:]\\s*(.*?)\\] did not take into account the colon in the ternary operator.

So, as shown in the picture, causing the problem.

Screenshot from 2022-09-22 12-42-26

To address this issue, VerilogPortParser and SystemVerilogExpressionParser have been improved, and test cases have been added to prove correctness.

Before fix:

Screenshot from 2022-09-23 04-48-12

After fix:

Screenshot from 2022-09-23 04-46-58

Test result about trinary operations:

...
PASS   : tst_SystemVerilogExpressionParser::testTrinaryOperations(Trinary 1?2:3 should be 2)
PASS   : tst_SystemVerilogExpressionParser::testTrinaryOperations(Trinary 1-1?2:3+1 should be 4)
PASS   : tst_SystemVerilogExpressionParser::testTrinaryOperations(Trinary ? should invalid)
PASS   : tst_SystemVerilogExpressionParser::testTrinaryOperations(Trinary : should invalid)
PASS   : tst_SystemVerilogExpressionParser::testTrinaryOperations(Trinary (3+2)?(4+6) should invalid)
PASS   : tst_SystemVerilogExpressionParser::testTrinaryOperations(Trinary (3+2):(4+6) should invalid)
PASS   : tst_SystemVerilogExpressionParser::testTrinaryOperations(Trinary (3+2)?((3+3)?(4+7):1):0 should be 11)
PASS   : tst_SystemVerilogExpressionParser::testTrinaryOperations(Trinary (1>2)?((3+3)?(4+7):1):0 should be 0)
PASS   : tst_SystemVerilogExpressionParser::testTrinaryOperations(Trinary 3+2?3+3?4+7:1:0 should be 11)
PASS   : tst_SystemVerilogExpressionParser::testTrinaryOperations(Trinary 1>2?3+3?4+7:1:0 should be 0)
PASS   : tst_SystemVerilogExpressionParser::testTrinaryOperations(Trinary 1?11:2?12:0 should be 11)
PASS   : tst_SystemVerilogExpressionParser::testTrinaryOperations(Trinary 1?11:(2?12:0) should be 11)
PASS   : tst_SystemVerilogExpressionParser::testTrinaryOperations(Trinary 1?12?1:0:22 should be 1)
...
PASS   : tst_SystemVerilogExpressionParser::cleanupTestCase()
Totals: 378 passed, 0 failed, 0 skipped, 0 blacklisted, 1428ms
********* Finished testing of tst_SystemVerilogExpressionParser *********
epekkar commented 2 years ago

Thanks vowstar. I did a little bit of extra cleaning on the expression parser after merging this one.